Digital phase control circuit

Details Digital phase control circuit Digital phase control circuit

2001-03-29

2002-12-10

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S237000, C327S231000, C327S261000

Reexamination Certificate

active

06492851

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a digital phase control circuit that receives reference clock signals having a prescribed frequency and outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal.
2. Description of the Related Art:
A digital phase control circuit that receives reference clock signals having a prescribed frequency and that outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal is configured similar to an example of the prior art, digital phase control circuit
100
, that is shown in FIG.
1
.
This digital phase control circuit
100
of the prior art is configured such that: input selector S
1
having four input terminals is connected to delay locked loop DLL
1
that includes a voltage-controlled delay line VCDL
1
that is composed of ten stages of differential buffers G
1
-G
10
and the differential buffer is a kind of delay buffer; and moreover, output selector S
2
is connected to the output of each of differential buffers G
1
-G
10
. Delay locked loop DDL
1
is composed of: voltage-controlled delay line VCDL
1
; phase detector PD
1
; charge pump CP
1
; and low-pass filter LPF
1
.
The composition and operation of this prior-art digital phase control circuit is next explained using numerical values.
Clock signals CLK
1
-
4
(reference clocks) of 325.5 MHz (with a period of 3200 ps) in a total of four phases with phase differences of 800 ps are supplied to the four input terminals IN of selector S
1
. In other words, two clock signals CLK
1
and CLK
3
having a half-period phase difference (1600 ps) with respect to each other form one differential pair, and similarly, another two clock signals CLK
2
and CLK
4
having a relative half-period phase difference (1600 ps) form a differential pair.
These clock signals CLK
1
-CLK
4
are controlled in advance by, for example, a phase-locked loop that is not shown in the figure such that the frequencies of the four clock signals CLK
1
-CLK
4
and the phase differences between them (800 ps) are equal and are then supplied to input terminals IN.
Selector S
1
selects and extracts a differential pair from the plurality of input terminals IN. In other words, selector S
1
selects a pair of differential clock signals from the four types of differential clock signals CLK
1
-
3
, CLK
3
-
1
, CLK
2
-
4
, and CLK
4
-
2
, and outputs to voltage-controlled delay line VCDL
1
and phase detector PD
1
.
In a case in which differential clock signals CLK
1
-
3
are selected, clock signal CLK
1
is outputted to one of the two output terminals OUT, and clock signal CLK
3
is outputted to the other.
The operation is equivalent in cases in which differential clock signals CLK
3
-
1
, CLK
2
-
4
, or CLK
4
-
2
are selected. However, the output terminals OUT to which differential clock signals CLK
1
and CLK
3
are outputted when differential clock signals CLK
1
-
3
are selected is the reverse of that for a case in which differential clock signals CLK
3
-
1
are selected. The same relation holds for differential clock signals CLK
2
-
4
and differential clock signals CLK
4
-
2
.
The ten stages of differential buffers G
1
-G
10
that make up voltage-controlled delay line VCDL
1
each have propagation delay times of 160 ps and are controlled by the feedback control of delay locked loop DLL
1
such that their delay times are uniform. The feedback control of delay locked loop DLL
1
is carried out as follows:
A clock signal having the total delay of all buffers G
1
-G
10
is outputted from differential buffer G
10
. In a case in which differential clock signals CLK
1
-
3
are selected by selector S
1
, for example, phase detector PD
1
both receives clock signals CLK
1
and CLK
3
that have passed through voltage-controlled delay line VCDL
1
and have the total delay of all buffers G
1
-G
10
and receives direct clock signals CLK
1
and CLK
3
(reference clocks) that have not passed through voltage-controlled delay line VCDL
1
. Phase detector PD
1
compares the phases of clock signal CLK
1
, which has the total delay, and clock signal CLK
3
(the reference clock) that precedes passage through voltage-controlled delay line VCDL
1
, compares the phases of clock signal CLK
3
having the total delay and clock signal CLK
1
(the reference clock) that precedes passage through voltage-controlled delay line VCDL
1
, and detects the phase differences. Phase detector PD
1
outputs an UP signal to charge pump CP
1
if the phase of clock signal CLK
1
(CLK
3
) having the total delay is behind the phase of clock signal CLK
3
(CLK
1
) that precedes passage though voltage-controlled delay line VCDL
1
; and outputs a DOWN signal to charge pump CP
1
if the phase of clock signal CLK
1
(CLK
3
) is ahead. The operation is equivalent for cases in which differential clock signals CLK
3
-
1
, CLK
2
-
4
or CLK
4
-
2
are selected by selector S
1
.
Charge pump CP
1
and low-pass filter LPF
1
generate control signals such that each buffer maintains a propagation delay time of 160 ps in accordance with the signals from phase detector PD
1
and sends these control signals to each of differential buffers G
1
-G
10
.
By means of this feedback control, the delay times of the ten stages of buffers in voltage-controlled delay line VCDL
1
are kept uniform. In other words, the period of 160 ps×10 stages=1600 ps is constantly corrected in voltage-controlled delay line VCDL
1
.
Clock signals having a resolution of 160 ps with respect to the reference clocks are outputted from output terminals OUT through the combination of selections of selectors S
1
and S
2
.
Taking for example a case in which differential buffer G
5
is selected by selector S
2
as the base state, the output delay of delay locked loop DLL
1
at this time will be the delay time 160 ps×5 stages 800 ps, if the delay of selectors S
1
and S
2
is ignored.
In contrast to this base state, the delay becomes 160 ps×6 stages=960 ps if differential buffer G
6
is selected by selector S
2
. In other words, delay (phase) is delayed with respect to the total delay of the basic state at a resolution of 160 ps.
Still further delay of the phase of the clock signal can be realized by selecting, by means of selector S
2
, a differential buffer having a higher number in delay locked loop DLL
1
. Conversely, an advance in the phase of the clock signal can be realized by selecting, by means of selector S
2
, a buffer having a lower number in delay locked loop DLL
1
. Thus, in digital phase control circuit
100
of the prior-art example, the delay (phase) resolution coincides with the propagation delay time (160 ps) of the buffers in voltage-controlled delay line VCDL
1
, i.e., resolution is determined by the buffer propagation delay time.
However, the prior art has the following problems:
Since resolution is determined by the propagation delay time of the buffers, the propagation delay time of the differential buffers must be decreased (made high-speed) to obtain a more minute resolution. However, there are limits to the buffer delay time, and currently, constructing buffers having a delay time of less than 50 ps is technologically extremely difficult. There is consequently the problem that a resolution smaller than the propagation delay time of a buffer cannot be obtained. Since the amount of phase control that is necessary for clock recovery for high-speed data of 2.5 Gbps is on the order of 40-50 ps, the realization of a digital phase control circuit that is capable of controlling phase at a resolution of less than 50 ps is crucial for realizing the high-speed data communication that is now being sought.
In addition, since feedback control is effected by delay locked loop DLL
1
such that the total delay of all buffers in voltage-controlled delay line VCDL
1
matches the delay (1600 ps) of half-period portions of the received ref

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