Digital phase alignment and integrated multichannel transceiver

Details Digital phase alignment and integrated multichannel transceiver Digital phase alignment and integrated multichannel transceiver

1995-04-11

1996-08-27

Chin, Wellington

Pulse or digital communications

Transceivers

Transmission interface between two stations or terminals

375356, 370105, H04L 2534

Patent

active

055508600

ABSTRACT:
A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

REFERENCES:
patent: 4916717 (1990-04-01), Sackman, III et al.
patent: 5117424 (1992-05-01), Cohen et al.
patent: 5408473 (1995-04-01), Hutchinson et al.
patent: 5481573 (1996-01-01), Jacobowitz et al.

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