Digital peak noise reduction circuit

Pulse or digital communications – Repeaters – Testing

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375 99, 364761, 364765, 377 47, H03K 2100, G06F 750, G06F 752

Patent

active

050238906

ABSTRACT:
A digital peak noise reduction circuit for reducing peak noise of an input digital signal having variable levels corresponding to a predetermined sound volume range. The circuit includes a division circuit for dividing the level of the input signal; a ROM for supplying a plurality of data expansion rates, each expansion rate being defined by a relationship between a different specific range of input digital signal level and the predetermined range; a multiplier for multiplying the digital audio data with the reciprocal related data output from the ROM; a multi-stage shift circuit for supplying a plurality of data compression rates, (each compression rate correspond to the expansion rates of the ROM) and for producing an output signal having a level corresponding to the selected compression rate; a de-emphasis circuit for compensating for specified frequency characteristics of the output signal; and a feedback circuit for supplying the output signal to the division circuit for controlling the ROM.

REFERENCES:
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patent: 4461025 (1984-07-01), Franklin
patent: 4573178 (1986-02-01), Morito
patent: 4701953 (1987-10-01), White
patent: 4707798 (1987-11-01), Nakano
patent: 4718032 (1988-01-01), Irukulla et al.
patent: 4785412 (1988-11-01), Tran
patent: 4941118 (1990-07-01), Yamazaki et al.
patent: 4949295 (1990-08-01), Stearns
Japanese Patent Disclosure (Kokai) No. 60-123931, K. Kawiwagi, Jul. 2, 1989.
"Digital Signal Processing System", Chap. 1, Sec. 3.3 Division To Kai Daigaku Syuppankai.

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