Digital overspeed controller for use in a vital processing syste

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36442401, 246182R, B61L 2300

Patent

active

049567799

ABSTRACT:
The functions to be performed by a digital overspeed controller are implemented by application of two concepts, namely "diverse channels" and "even/odd systems cycles"; in accordance with the first concept, two channels are maintained throughout the overspeed controller, beginning with two independent tachometer inputs; all of the functions involve operations to be performed in each of the two channels separately. The numerical results for each of the channels are different and the numerical difference between the two channels is used to prove the integrity of the functions described. The second concept of "even/odd system cycles" involves a "system cycle time", denoted T.sub.CYC, that is nominally 100 milliseconds. All of the functions of the controller are performed each system cycle. In order to be able to vitally distinguish data results between adjacent cycles, the cycles are denoted EVEN and ODD, and the results of each of the operations produce different numerical values on even and odd cycles.

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