Digital offset phase-locked loop

Details Digital offset phase-locked loop Digital offset phase-locked loop

2008-12-22

2010-06-29

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S018000, C331S025000, C331S030000

Reexamination Certificate

active

07746178

ABSTRACT:
The present invention relates to a digital offset phase-locked loop (DOPLL), which may have advantages of size, simplicity, performance, design portability, or any combination thereof, compared to analog-based phase-locked loops (PLLs). The DOPLL may include a digital controlled oscillator (DCO), which provides a controllable frequency output signal based on a digital control signal, a radio frequency (RF) mixer circuit, which provides a reduced-frequency feedback signal based on the controllable frequency output signal without reducing loop gain, a time-to-digital converter (TDC), which provides a digital feedback signal that is a time representation of the reduced-frequency feedback signal, and digital PLL circuitry, which provides the digital control signal based on the digital feedback signal and a digital setpoint signal.

REFERENCES:
patent: 2010/0033220 (2010-02-01), Zhang

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