Digital non-integer sample/hold implemented using virtual...

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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C341S155000

Reexamination Certificate

active

11478275

ABSTRACT:
A method and apparatus for implementing non-integer sample hold operations in a sigma-delta digital-to-analog converter system includes an interpolation filter, a polyphase filter circuit, and a modulator. The polyphase filter circuit is used to virtual upsample a digital input signal by a predetermined non-integer upsample ratio of a relatively large number. The polyphase filter circuit is formed of a long zero-order hold and a short FIR filter so that only several branches associated with the polyphase filter circuit corresponding to output samples immediately after a transition of the digital input signal is required to be calculated, thereby reducing the need to store a large number of filter coefficients and eliminating complex computations.

REFERENCES:
patent: 7038711 (2006-05-01), Albright
patent: 7136430 (2006-11-01), Morris et al.
patent: 7167113 (2007-01-01), Azizi
patent: 7176820 (2007-02-01), Fuller et al.
Ronald E. Crochiere and Lawrence R. Rabiner, “Interpolation and Decimation of Digital Signals—A Total Review”, Proceeding of the IEEE, Mar. 1981, p. 300-331,vol. 69, No. 3.
S. Harris, G. Kamath and E. Gaalaa, “A Monolithic 24-Bit, 96kHz Sample Rate Converter with AES3 Receiver and AES3 Transmitter”, presented at AES 105th Convention, San Fransico, CA, 1998.

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