Digital noise reduction through selective pixel comparison

Details Digital noise reduction through selective pixel comparison Digital noise reduction through selective pixel comparison

1999-10-15

2003-04-08

Do, Anh Hong (Department: 2624)

Image analysis

Image enhancement or restoration

Artifact removal or suppression

C382S172000, C382S270000

Reexamination Certificate

active

06546149

ABSTRACT:

TECHNICAL FIELD
This invention is directed to reducing noise in the conversion of an analog signal to a digital video signal and, in particular, by using a subset of a total image to determine the noise level of a static image over a period of time.
BACKGROUND OF THE INVENTION
It has become increasingly popular to use multimedia display systems to make presentations at business meetings, sales demonstrations, and classroom sessions. Most multimedia projection display systems receive analog video signals from a personal computer (PC). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control a digitally-driven display object, such as a transmissive liquid crystal display (LCD) or a digital mirror device (DMD), to form the display images for projection onto a display screen.
Two common types of multimedia projection display systems are LCD projectors and LCD projection panels. An LCD projector includes a transmissive LCD, a light source, and projection optics to form ad project display images in the manner described above. An LCD projection panel includes a similar transmissive LCD to form the display image, but operates with a conventional overhead projector (OHP) having a light source and projection optics, to project the display image onto a display screen. Examples of such LCD projectors and LCD projection panels are sold under the respective trademarks LITEPRO and PANELBOOK by In Focus Systems, Inc. of Wilsonville, Oreg., the assignee of the present invention.
One desirable feature for multimedia display systems is compatibility with the various analog video signal modes generated by various PC's. These modes generally range from 640×480 to 1600×1200 resolutions provided at image refresh rates of 60 to 100 Hz. The resolution expresses the number of horizontal and vertical pixel elements that can be turned on and off. Given the variety of resolution modes, multimedia display systems include an interface that converts analog video signals of various modes to digital video signals capable of controlling the LCD.
Analog video signals comprise an analog image data signal for each of the primary colors red, green and blue, and digital timing signals, which may include a pulsed horizontal synchronizing signal (Hsync) and a pulsed vertical synchronizing signal (Vsync), or a composite sync signal. The individual analog color signals are generated from bit data in a memory portion of the PC, using three digital-to-analog (D/A) converters, one for each of red, green, and blue. A complete image is typically displayed during a time interval known as a “frame period.” Each video frame is usually produced to have a central active video region surrounded by an inactive (“blanked”) margin. The resolution refers to only the pixels in the active video region. The state of each pixel, it's color or shade of gray, for example, is described by several bits of data. The exact number of bits depends upon the desired number of colors or gray levels. Because of the large number of pixels and multiple bits required to specify the optical state of each pixel, a large amount of image data is required to characterize the image of each frame. For example, a typical liquid crystal display may have 480 rows and 640 columns that intersect to form a matrix of 307,200 pixels.
Because the LCD used in multimedia display systems require digital video signals, either the LCD or the system normally has an analog to digital (A/D) signal converter for converting the PC-generated analog video signals into a digital format suitable for driving the LCD. The A/D signal converter is usually combined with a phase-locked loop (PLL), which may comprise a phase comparator, a low-pass loop filter, and a voltage-controlled oscillator (VCO) formed in a loop to generate a feedback signal that locks into Hsync. In order to generate a selected multiple n of clock pulses for each period of Hsync, a divide-by-n counter is added to the feedback loop between the VCO output and the phase comparator.
The number n of individual pixel pulses per Hsync pulse may be set by reference to the resolution mode of the analog video source. To set the resolution mode, certain characteristics of the analog video signal, such as Hsync and Vsync may be used to refer to a mode look-up table stored in the display system CPU. The number n should be set to equal the number of pixel data components in each horizontal line of the scanned analog signal, including those active video data region and the blanked margin regions on either side of the active region. For example, for a screen resolution of 640×480, n may be set at about 800 to include the blanked regions on either side of the 640 pixel-wide active video data region. Thus, the pixel clock would sample the continuous stream of analog image data 800 times along each horizontal line of the frame.
FIG. 1
shows the desired relationship between the analog video data signal
1
and the pixel clock signal
4
is that the number n of pixel clocks
5
is set to establish a one-to-one relationship between pixel clock pulses
5
and pixel data components
2
of the analog data signal
1
. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video data signal frequency. Under this relationship, each pixel data component
2
of the analog signal is sampled by a single pixel clock pulse
5
, which reads the instantaneous voltage value of the pixel data component so that it can be digitized. Since the pixel clock pulses
5
have “jitter” zones
6
at their leading and trailing edges, the clock pulses
5
should be registered with the centers of the pixel data components
2
, so that the sampling is not randomly pushed by the jitter into the transition regions of the analog video signal. The stream of digitized values form the digital video data signal, which is addressed to the display object to appropriately set display object pixels at blank (black) or selected activated (non-black) status to replicate the image defined by the analog video signal.
Unfortunately, such A/D conversion is often imperfect due to errors in the pixel clock sampling of the analog signal. Such sampling imprecision gives rise to frequency (also known as “tracking”) and “phase” errors, both of which may degrade the quality of the image.
Referring to the analog video signal
1
and pixel clock signal
4
′ in
FIG. 2
, tracking error results from the number n of pixel clocks being improperly set. As discussed above, the number n of pixel clocks should be equal to the number of pixel data components
2
of each horizontal line of analog video data signal. In
FIG. 2
, the improper setting of n results in the pixel data components
2
not being sampled at a consistent point. For instance, n is set too large in clock signal
4
′. The resulting crowding of the pixel clock pulses
5
′ yields an additive leftward drift of the pixel clock pulses
5
′ relative to the pixel clock data components
2
of the analog video data signal
1
. Such drift causes sampling in the transition regions
3
. For instance, as indicated by positional bracket A, the leading edges
7
′ of the third through the sixth clock pulses
5
′ sample in transition zones
3
of the analog video signal
1
.
Accordingly, the transition zone data will be erroneous and the image information from adjacent non-sampled pixel data components
2
will be missing from the digitized video signal. If n is erroneously set large enough, the pixel clock pulses may be so crowded that individual analog pixel data components
2
may be double-sampled. On the other hand, if n is set too small, the dispersion of the pixel clock pulses results in a rightward drift wherein sampling may also occur in the transition regions. In all of these cases, the erroneous sampling provides erroneous video signal data that may degrade the image quality.
Phase error may occur even if

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