Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-10-06
2001-03-20
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06205462
ABSTRACT:
TECHNICAL FIELD
The present invention relates to Multiply-Accumulate circuits, and more particularly to a circuit that can directly receive two operands in both integer and floating point data formats, multiplies the two operands, and accumulates the resultant product.
BACKGROUND ART
FIG. 3
shows a typical digital Multiply-Accumulate circuit
50
of the prior art. Registers
52
and
54
hold two operands to be operated on. These two operands must be in the same data format, i.e. both must be either integers or floating point numbers. The two operands are multiplied in multiplier
56
and the resultant product is inputted into adder
58
as a first input. A second input of adder
58
comes from accumulator
60
. The resultant sum of the two inputs generated by adder
58
will replace the current content of accumulator
60
. Another pair of operands may be loaded into registers
52
and
54
. Their product generated by multiplier
56
is accumulated by adder
58
into accumulator
60
. So, accumulator
60
holds the sum of products of pairs of operands. For that reason, circuit
50
is also called a product adder.
A typical digital Multiply-Accumulate circuit as shown in
FIG. 3
cannot operate on both integer and floating point numbers simultaneously. When a computation involves operands of both integer and floating point numbers, a separate converting circuit is used. The converting circuit may be of integer-to-floating-point type in which the integer is converted into a floating point number before being loaded into the floating point Multiply-Accumulate circuit to be multiplied with another floating point number.
FIG. 4
shows a typical Integer to Floating Point converting circuit of prior art. This circuit is disclosed and described in detail in U.S. Pat. No. 4,631,696. The 32-bit integer to be converted to floating point number is in register
11
. Zero detectors Z
0
to Z
7
detects leading zeros of the integer. Priority encoder
13
receives the detection results from Zero detectors Z
0
to Z
7
and determines the necessary number of shifting places for the integer. Shifter
15
shifts the integer according to the control input LZ from priority encoder
13
producing the 24-bit mantissa. The detected number of leading zeros of the integer is used to calculate the 7-bit offset exponent using adder
14
.
An object of the present invention is to provide a Multiply-Accumulate circuit that can accept operands of both integer and floating point numbers, but does not require much additional circuitry. Another object of the present invention is to use only one instruction set for operations on both integer and floating point numbers.
DISCLOSURE OF THE INVENTION
The Multiply-Accumulate circuit of the present invention realizes these objects by providing that operands of both integer and floating point numbers are represented in a special combined data format. This special combined data format allows for the circuit of the present invention. The format prescribes an exponent and a mantissa for both integer and floating point numbers. Floating point numbers still keep their original format, i.e. mantissa and exponent, except that floating point numbers with exponent having all zeros or all ones are defined to be invalid and are replaced with other close values which have exponents being not all ones or zeros. Number representations with exponents being all ones or all zeros are reserved for integer numbers.
The Multiply-Accumulate circuit of the present invention includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in the special combined data format. The exponent adder circuit adds the exponents of the two operands in the special combined data format. But if, before the addition, the exponent adder circuit detects an integer as an operand, it will replace the exponent of the integer with a substitute value in that addition. This substitute value is the number of bits of the mantissa of the integer. This replacement has the effect of implicitly converting the integer into a floating point number. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sun of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.
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patent: 4620292 (1986-10-01), Hagiwara et al.
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patent: 4805128 (1989-02-01), Nelsen et al.
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patent: 5185713 (1993-02-01), Kobunaya
patent: 5257215 (1993-10-01), Poon
patent: 5272654 (1993-12-01), Nix
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Harrison David A.
Wyland David C.
Cradle Technologies
Mai Tan V.
Schneck Thomas
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