Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-04-17
2007-04-17
Malzahn, D. H. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
10437502
ABSTRACT:
A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit. The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders are low. The Latch Adders may be controlled by Control Signals, which may be generated by Control Circuits. The application of the Latch Adders may be applied to the Final Stage Adder Circuit to further reduce spurious switching and thereby further reduce the power dissipation.
REFERENCES:
patent: 3657635 (1972-04-01), Quinn
patent: 4559608 (1985-12-01), Young et al.
patent: 4982355 (1991-01-01), Nishimura et al.
patent: 5333119 (1994-07-01), Raatz et al.
patent: 5367691 (1994-11-01), Johnson
patent: 5448639 (1995-09-01), Arazi
patent: 5734601 (1998-03-01), Chu
patent: 5787029 (1998-07-01), de Angel
patent: 5818743 (1998-10-01), Lee et al.
patent: 5924050 (1999-07-01), Maruyama
patent: 6021424 (2000-02-01), Chu
patent: 6898613 (2005-05-01), Robinson et al.
C.S. Wallace, “A Suggestion for a Fast Multiplier”; IEEE Transactions On Electronic Computers; pp. 14-17; 1964.
J.F. Wakerly, “Section 5.10 Adders, Subtractors, and ALUs”; Digital Design Principles & Practices, 3rd Ed., Prentice Hall, 2000, pp. 430-453.
W. J. Dally, et al., “Chapter 10 Synchronization”; Digital Systems Engineering, Cambridge University Press, 1998, pp. 462-513.
Fang Lu, et al., “A 200-MHz CMOS Pipelined Multiplier—Accumulator Using a Quasi-Domino Dynmic Full-Adder Cell Design”; IEEE Journal of Solid State Circuits, vol. 28, No. 2, Feb. 1993, pp. 123-132.
C. Lemonds, et al., “A Low Power 16 by 16 Multiplier Using Transition Reduction Circuitry”; International Workshop on Low Power Design, Apr. 1994, pp. 139-142.
Chang Joseph Sylvester
Chong Kwen Siong
Gwee Bah Hwee
Chang, Joseph Sylvester
Gwee, Bah Hwee
Malzahn D. H.
Osha & Liang LLP
LandOfFree
Digital multiplier with reduced spurious switching by means... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital multiplier with reduced spurious switching by means..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital multiplier with reduced spurious switching by means... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3776354