Digital multiplier circuit and a digital multiplier-accumulator

Details Digital multiplier circuit and a digital multiplier-accumulator Digital multiplier circuit and a digital multiplier-accumulator

1987-11-09

1990-09-18

LaRoche, Eugene R.

Boots, shoes, and leggings

364736, G06F 748

Patent

active

049583123

ABSTRACT:
Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.

REFERENCES:
patent: 4215416 (1980-07-01), Muramatsu
Paper entitled "A Suggestion for a Fast Multiplier", by C. S. Wallace, IEEE Transactions on Electronic Computers, Feb., 1964, pp. 14-17.
Article entitled "A CMOS 32b Wallace Tree Multiplier-Accumulator", by Abbas El Gamal, et al., IEEE International Solid State Circuits Conference, Feb. 20, 1986, pp. 194-195, also p. 345.
Book entitled Introduction to Arithmetic for Digital Systems Designers, Schlomo Wasser, et al., 1982 CBS Publishing, 383 Madison Ave., New York, NY 10017, p. 15.
Paper entitled "A NMOS LSI 16X16 Multiplier", by Norman C. Wittmer et al., IEEE International Solid-State Circuits Conference, Feb. 23, 1983, pp. 32 and 33.

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