Digital multiplier based upon a regularly structured sum of prod

Details Digital multiplier based upon a regularly structured sum of prod Digital multiplier based upon a regularly structured sum of prod

1992-01-28

1993-07-27

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

052316017

ABSTRACT:
A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.

REFERENCES:
patent: 4130877 (1978-12-01), Riekers
patent: 4293922 (1981-10-01), David et al.
patent: 4752905 (1988-06-01), Nakagawa et al.
patent: 4852037 (1989-07-01), Aoki
patent: 4910700 (1990-03-01), Hartley et al.
patent: 4939687 (1990-07-01), Hartley et al.
Stearns et al., "Yet Another Multiplier Architecture", Proceedings of the IEEE 1990, Custom Integrated Circuits Conference, May 13-16, 1990, pp. 24.6.1-24.6.4.
Roberts et al., "A 2.5 nS ECL 16.times.16 Multiplier", Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, May 13-16, 1990, p. 24.7.1.

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