Digital multiplier

Details Digital multiplier Digital multiplier

1975-06-02

1977-03-22

Smith, Jerry

Registers

Transfer mechanism

Traveling pawl

G06F 752

Patent

active

040138798

ABSTRACT:
The digital CMOS/LSI synchronous serial multiplier includes a register to store an X-bit sign magnitude multiplier in parallel. The digital multiplier number can be entered into the register either serially or in parallel. A serial N-bit 2's complement multiplicand input is provided. (X - 1) adder stages are connected in series. A control arrangement coupled to the register, the multiplicand input and the adder stages are provided to couple each of the magnitude bits of the multiplier number into a different one of the adder stages with the adder stages performing successive additions of the magnitude bits of the multiplier number to provide as an output of a last of the adder stages a serial product having M bits. A serial Y-bit 2's complement addend can be coupled to the first of the adder stages to add the addend to the product.

REFERENCES:
patent: 3610907 (1971-10-01), Taylor
patent: 3617723 (1971-11-01), Melvin
patent: 3805043 (1974-04-01), Clary
patent: 3816732 (1974-06-01), Jackson
patent: 3885141 (1975-05-01), Kieburtz

Affiliated with

Also associated with

Rating

Digital multiplier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital multiplier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital multiplier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1957871