Digital multiplier

Details Digital multiplier Digital multiplier

1992-04-10

1993-10-12

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

052531945

ABSTRACT:
A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.

REFERENCES:
patent: 4546446 (1985-10-01), Machida
patent: 4831577 (1989-05-01), Wei et al.
patent: 5070471 (1991-12-01), Dao-Trong et al.

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