Digital multi-tapped delay line with automatic time-domain progr

Details Digital multi-tapped delay line with automatic time-domain progr Digital multi-tapped delay line with automatic time-domain progr

1981-09-18

1984-04-17

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

328119, 377 76, 377 81, 307602, H03K 5159, H03K 514

Patent

active

044437650

ABSTRACT:
A single-input, multiple-output device which enables an electrical signal be automatically delayed in accordance with irregularly spaced synchronization pulses. The device employs a plurality of first-in, first-out (FIFO) shift registers energized in inverse order by the clocked outputs of a series of conventional shift registers. The signal to be delayed is stored in the FIFO registers and read out in accordance with the sequence of synchronization pulses provided to the conventional registers.

REFERENCES:
patent: 3184685 (1965-05-01), Funk et al.
patent: 3588707 (1971-06-01), Manship
patent: 3675049 (1972-07-01), Haven
patent: 3728635 (1973-04-01), Eisenberg
patent: 4016511 (1977-04-01), Ramsey et al.

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