Digital microprocessor having a time-shared adder

Details Digital microprocessor having a time-shared adder Digital microprocessor having a time-shared adder

1979-03-08

1981-01-06

Malzahn, David H.

Boots, shoes, and leggings

364900, G06F 750

Patent

active

042440289

ABSTRACT:
The disclosed microprocessor time-shares an adder with a data memory, an accumulator, an I/O register, and an edge detector. This time-sharing is synchronized by a timing generator that produces interleaved first and second clocked pulses. Instructions are fetched from an instruction memory during the first clock pulses and are performed during the second clock pulses. To perform these instructions, the contents of the data memory and the accumulator are passed through the adder and fed back to the accumulator. In addition, during the first clock pulses, the contents of the I/O register and the output of the edge detector are passed through the adder and fed back to the I/O register. This allows the I/O register to be used as a counter while simultaneously allowing the structure of the I/O register to be greatly simplified.

REFERENCES:
patent: 3980992 (1976-09-01), Levy et al.
patent: 3990052 (1976-11-01), Gruner
patent: 4021656 (1977-05-01), Caudel et al.
patent: 4144563 (1979-03-01), Heuer et al.

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