Boots – shoes – and leggings
Patent
1996-05-07
1998-09-08
Ngo, Chuong Dinh
Boots, shoes, and leggings
G06F 752
Patent
active
058054898
ABSTRACT:
The present invention is a variable-delay division (VDD) scheme implementable in hardware to execute signed and unsigned integer division and remainder operations in digital processor. The VDD scheme advantageously uses hardware utilized for multiplication to implement a 2-bits/cycle alignment step to iteratively align the divisor with the dividend. This speeds up the alignment phase of integer division. Quotient bits are produced at the rate of 1-bit/cycle using the well-known restoring scheme. For 32-bit 2's complement operands, the scheme has a delay less than a fixed-delay scheme for most operands.
REFERENCES:
patent: 5097435 (1992-03-01), Takahashi
patent: 5301139 (1994-04-01), Zinger
patent: 5493523 (1996-02-01), Huffman
Lucent Technologies - Inc.
Ngo Chuong Dinh
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