Digital method and device for correcting the phase error of a sa

Details Digital method and device for correcting the phase error of a sa Digital method and device for correcting the phase error of a sa

1982-07-19

1985-03-05

Murray, Richard

Facsimile and static presentation processing

Static presentation processing

Attribute control

358339, H04N 932

Patent

active

045034532

ABSTRACT:
At the time of analog-to-digital conversion by sampling of a sine-wave signal having a frequency F by means of a clock signal having a frequency 4nF where n is a whole number, these two signals exhibit a residual phase error .PHI.. The method for correcting the converted digital signal according to the invention consists in delaying this signal by n periods of the clock signal in a shift register, in multiplying the undelayed signal by cos .PHI., in multiplying the delayed signal by sin .PHI. and in transmitting the results to an adder.

REFERENCES:
patent: 4122487 (1978-10-01), Beaulier et al.
patent: 4301466 (1981-11-01), Lemoine et al.
patent: 4349833 (1982-09-01), Clarke

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