Digital memory system utilizing fast and slow address dependent

Details Digital memory system utilizing fast and slow address dependent Digital memory system utilizing fast and slow address dependent

1983-05-11

1984-10-23

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 1300

Patent

active

044791801

ABSTRACT:
An improved addressing circuit for memory system using a plurality of integrated circuit memory arrays is disclosed. Typical integrated digital memory arrays include an address input which accepts a digital signal which identifies the storage locations in the array and an array enable input signal. In typical arrays, the time to respond to the address input signals and the array input signal is different with decoding of the array enable signal typically being considerably faster than decoding of the address signal. In the disclosed addressing scheme, the arrays comprising the system are arranged such that a first portion of the system address signal is decoded to select the array with the remainder of the address portion serving to select the storage location within the selected array. The addressing is arranged such that for a sequentially addressed data block, a word is read from each of the arrays before the address inputs to the arrays is changed. This causes the memory access time to be considerably improved because the array input enable signals are normally decoded much faster than the address inputs.

REFERENCES:
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patent: 4079454 (1978-03-01), Sorenson et al.
patent: 4080659 (1978-03-01), Francini
patent: 4095269 (1978-06-01), Kawabe et al.
patent: 4155118 (1979-05-01), Lamiaux
patent: 4285039 (1981-08-01), Patterson et al.

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