Digital memory providing fixed and variable delays in a TASI sys

Details Digital memory providing fixed and variable delays in a TASI sys Digital memory providing fixed and variable delays in a TASI sys

1979-01-12

1981-08-18

Robinson, Thomas A.

Multiplex communications

Wide area network

Packet switching

H04J 500

Patent

active

042848504

ABSTRACT:
A time assignment speech interpolation system has a random access memory which provides both a fixed and a variable delay between an input speech channel and a transmission facility. Digital samples of the signal detected on an input speech channel are stored for a fixed time in a portion of the memory in order to provide time for switching without clipping and for generation of a channel identifying symbol. If a transmission facility is available, the sample is read out of memory after the fixed delay and reconstituted into an analog signal which is transmitted on the available facility. If no transmission facility is available, the samples are read out of memory after the fixed delay and written into another portion of memory which stores them for variable times until a transmission facility is available. In one embodiment, the portions of the memory assigned to providing variable delay are paired. Starting addresses are at the two extremes of memory locations in a pair, and successive memory locations extend toward the other extreme starting address. In another embodiment, the memory assigned to providing variable delay is segmented. As one segment is filled, it is linked to another available segment. In this embodiment, silence purging logic may also be provided which determines whether any of the samples stored in particular segments represent silence or pauses in the stored speech. If they do, these segments are then classified as available.

REFERENCES:
patent: 3644680 (1972-02-01), Amano et al.
patent: 3836719 (1974-09-01), Clark
patent: 4012595 (1977-03-01), Ota
patent: 4048447 (1977-09-01), Maruta

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