Digital memory color framing circuit

Details Digital memory color framing circuit Digital memory color framing circuit

1983-02-28

1985-07-23

Murray, Richard

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 17, H04N 932

Patent

active

045311471

ABSTRACT:
The invention provides a color framing circuit for a digital memory, which has a first read line flip-flop generator for producing an RLFF.sub.0 pulse; a toggle flip-flop for receiving a loading data from a memory using a vertical pulse or a delayed (1H) vertical pulse as a load timing pulse only when the RLFF.sub.0 pulse is high and for producing an output signal (RLFF.sub.1 pulse); a vertical selector for selecting one of the vertical pulse and the delayed vertical pulse when the output signal from the toggle flip-flop is high; a read address counter for producing an address signal; and a blanking/burst generator for receiving the RLFF.sub.0 and RLFF.sub.1 pulses as control pulses, thereby receiving as a read address signal the address signal from the address counter. An output video signal phase offset is decreased corresponding to a range of 140 ns (peak-to-peak), and one of the address counters is eliminated.

REFERENCES:
patent: 4122477 (1978-10-01), Gallo

Affiliated with

Also associated with

Rating

Digital memory color framing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital memory color framing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital memory color framing circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-636645