Digital matched filter circuit employing analog summation

Details Digital matched filter circuit employing analog summation Digital matched filter circuit employing analog summation

2000-02-16

2003-12-16

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S149000, C375S150000, C375S152000

Reexamination Certificate

active

06665358

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a digital matched filter useful for acquiring synchronization in, for example, a receiver in a code division multiple access communication system.
Code division multiple access (CDMA) is a spread-spectrum communication technique in which a transmitted data signal is spread and despread by a cyclically repeating code, referred to below as a pseudorandom noise code or PN code. To despread a received CDMA signal, the receiver must generate the same PN code as used to spread the signal at the transmitter, in precise synchronization with transmitter's PN code. Before communication can begin, accordingly, the receiver must acquire synchronization with the transmitter's PN code.
To enable synchronization to be acquired, the transmitter commonly transmits a pilot signal or training signal identical to the PN code itself. A fast method of acquiring synchronization employs a matched filter that correlates the received signal with the known waveform of the PN code, or some part thereof.
A PN code can be represented as a series of chips with values of plus or minus one. In this case, a matched filter can be conceptually represented as in
FIG. 1
by a tapped delay line
2
with a first set of taps coupled to a first adder
4
and a second set of taps coupled to a second adder
5
. A third adder
6
subtracts the sum of the second set of tapped outputs from the sum of the first set of tapped outputs. If the total number of taps is sufficiently large, then the output of the third adder
6
will be very large when the positions of the +1's in the received PN code correspond to the positions of the first set of taps, and the positions of the −1's correspond to the positions of the second set of taps. In other cases, the output of adder
6
will be close to zero. This type of matched filter enables synchronization to be acquired in a period equal, at most, to one complete cycle of the PN code, provided the filter output can be obtained in real time.
To obtain real-time output, the received signal is conventionally supplied as an analog signal to a charge-coupled device (CCD) or a surface-acoustic-wave (SAW) device, which functions as the tapped delay line
2
.
FIG. 2
shows an equivalent representation of a SAW device in which taps are represented by variable resistances R spaced at delay intervals D equivalent to one chip of the PN code. The tapped outputs are summed in an analog fashion, simply by being coupled in parallel to the same output line.
A disadvantage of using a CCD or SAW device as a matched filter is that the device is a discrete device, which takes up space and cannot easily be integrated with other signal-processing circuitry. This is especially true when the other signal-processing circuitry requires input of the received signal in digital form, as is often the case in CDMA receivers.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a method of correlating a digital input signal with a known code in real time.
Another object of the invention is to provide a digital matched filter implementing the invented method.
The invented method stores a series of values of a digital input signal in a memory, compares each stored value with a corresponding value of the known code, and generates an analog comparison result signal for each comparison. The analog comparison result signals are combined to obtain an analog sum signal, which is then converted to a digital output signal.
In one type of digital matched filter implementing the invented method, the analog comparison result signals are current signals generated by switching current sources on and off. The current signals are combined by being supplied in parallel to a common terminal. A current mirror may be used to obtain the analog sum signal by amplifying the combined current signal.
In another type of digital matched filter implementing the invented method, the analog comparison result signals are voltage signals represented by charges stored in capacitors, which are individually charged or discharged according to the comparison results. The analog sum signal is obtained by interconnecting the capacitors, thereby averaging the stored charge.
The invented digital matched filters provide output in real time because the operation of combining the analog comparison result signals into an analog sum signal involves substantially no processing delay.
The circuits that generate and combine the analog comparison result signals have an essentially digital configuration, comprising transistors that are switched on and off, so the invented digital matched filters can easily be integrated with other digital signal-processing circuits.


REFERENCES:
patent: 5995046 (1999-11-01), Belcher et al.
patent: 6301294 (2001-10-01), Hara et al.
“Supekutoramu Kakusan Tsushin” (Spread-Spectrum Communication), Yukiji Yamauchi, Tokyo Electrical University, 1994, pp. 105-112.

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