Digital matched filter

Details Digital matched filter Digital matched filter

2000-06-02

2004-08-10

Chaki, Kakali (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S300000

Reexamination Certificate

active

06775684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital matched filter for use in a receiver or the like for spread-spectrum communication.
2. Description of the Prior Art
A method of data communication called spread-spectrum communication is known in which a transmitter transmits data signals after multiplying them by wide-band diffusion codes and a receiver restores the received signals to their original form, narrow-band signals, through back-diffusion. This method permits detection of data signals even when the carrier-to-noise ratio of received radio-wave signals is poor, and is thus regarded as a promising data communication method in code division multiple access, which is one form of multiple access for a mobile communication system.
In spread-spectrum communication, to restore received diffused data to its original form through back-diffusion, it is essential to synchronize the received data with the back-diffusion codes. As an index with which to achieve this synchronization, the correlation value between the received data and the back-diffusion codes is used. Here, the correlation value refers to the sum, at a given phase, of the products of the individual signals constituting the received data and the corresponding back-diffusion codes. This correlation value, at a phase at which the received data is synchronized with the back-diffusion codes, takes the maximum value among the correlation values at different phases. Accordingly, by detecting the phase at which the correlation value takes the maximum value, it is possible to synchronize the received data with the back-diffusion codes. One known method of calculating the correlation value at a given phase is to use a matched filter.
FIG. 7
shows an example of the configuration of a conventional digital matched filter. In this figure, reference numerals
1
to
8
represent delay devices, each outputting the data input thereto with a delay, that are connected in series in such a way that the data input to one delay device is shifted to the next in synchronism with the rising edges of a clock. Reference numerals
9
to
16
represent multipliers, each multiplying the output from corresponding one of the delay devices
1
to
8
by corresponding one of codes
1
to
8
. Here, the codes
1
to
8
each take a value of either “1” or “0”, and the multipliers
9
to
16
are each so configured as to multiply the output from the corresponding delay device by 1 or −1 according to whether the corresponding code equals “0” or “1”, respectively. Reference numeral
17
represents an adder, which adds together the outputs from all the multipliers
9
to
16
and then outputs the result as output data.
Suppose that, as shown in
FIG. 8
, a lapse of time is divided into time intervals T
1
, T
2
, T
3
, . . . in a way that correspond to the rising edges of the clock. Then, the contents of the delay devices
1
to
8
and of the codes
1
to
8
in each of those time intervals are as shown in FIG.
9
. Where input data D
1
, D
2
, D
3
, . . . is shifted from one of the delay devices
1
to
8
to the next, back-diffusion codes S
1
to S
8
remain still in the codes
1
to
8
, respectively. Meanwhile, the correlation value between the input data and the back-diffusion codes is calculated in the following manner. Suppose that input data (Da, Db, Dc, Dd, De, Df, Dg, Dh) has been received in this order chronologically and, as a result, the delay devices
1
to
8
now output data Dh, Dg, Df, De, Dd, Dc, Db, and Da to the multipliers
9
to
16
, respectively. Then, the adder
17
outputs, as output data, Dh×S
1
+Dg×S
2
+Df×S
3
+De×S
4
+Dd×S
5
+Dc×S
6
+Db×S
7
+Da×S
8
.
However, in this configuration, input data is shifted in all of the delay devices
1
to
8
at every rising edge of the clock, and thus the amount of change in signals per unit time interval is considerably great, which means that a large amount of electric power is consumed. Although
FIG. 7
shows an example in which only eight delay devices are used, in practical applications it is necessary to use hundreds of delay devices, and therefore a huge amount of electric power is consumed.
To solve this problem, Japanese Patent Application Laid-Open No. H10-173485 proposes a method that does not require the shifting of input data. An example of the configuration of a digital matched filter exploiting this method is shown in FIG.
10
. In this figure, reference numerals
1
to
8
represent delay devices, each holding the data input thereto, that are connected in parallel in such a way as to hold the data fed thereto in synchronism with the rising edges of clocks
1
to
8
, respectively.
Reference numerals
9
to
16
represent multipliers, each multiplying the output from corresponding one of the delay devices
1
to
8
by corresponding one of codes
1
to
8
. Here, the codes
1
to
8
each take a value of either “1” or “0”, and the multipliers
9
to
16
are each so configured as to multiply the output from the corresponding delay device by 1 or −1 according to whether the corresponding code equals “0” or “1”, respectively. Reference numeral
17
represents an adder, which adds together the outputs from all the multipliers
9
to
16
and then outputs the result as output data.
As shown in
FIG. 11
, the clocks
1
to
8
are so produced that only one of them has a pulse in a given time interval, and thus each of the clocks
1
to
8
has one-eighth of the frequency of the clock shown in FIG.
8
. Here, the contents of the delay devices
1
to
8
and of the codes
1
to
8
in each of consecutive time intervals are as shown in FIG.
12
. Whereas input data D
1
, D
2
, D
3
, . . . remains held in fixed ones of the delay devices
1
to
8
, back-diffusion codes S
1
to S
8
are shifted from one of the codes
1
to
8
to the next. Meanwhile, the correlation value between the input data and the back-diffusion codes is calculated.
In this configuration, back-diffusion codes need to be shifted, but input data, by being held in fixed delay devices, does not need to be shifted. In general, back-diffusion codes consist of fewer bits than input data. Accordingly, this method, requiring the shifting of back-diffusion codes but not the shifting of input data, helps reduce the amount of change in signals per unit time interval and thereby reduce electric power consumption.
However, in this configuration, to specify in which delay devices to hold input data, it is necessary to use as many clocks as the number of back-diffusion codes used; that is, in practical applications, it is necessary to use hundreds of clocks. This requires not only a large-scale clock generator circuit, but also a large area for conductor patterns for clocks. Moreover, input data needs to be fed to all delay devices simultaneously, and therefore the line for feeding input data needs to have a high load capacity, which leads to increased electric power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a digital matched filter that makes it possible to reduce the amount of change in signals per unit time interval, reduce the number of clocks needed, and minimize the increase in the load capacity of a data input line.
To achieve the above object, according to the present invention, a digital matched filter is provided with: a serial-to-parallel conversion circuit for converting serial data fed thereto into n sets of parallel data (where n is a natural number); m-stage delay circuits (where m is a natural number), connected in series and provided as stages following the serial-to-parallel conversion circuit, each outputting the n sets of parallel data fed thereto with a delay corresponding to n sets of data; and a correlation value calculation circuit for calculating the correlation value between n×(m+1) sets of data output individually from the serial-to-parallel conversion circuit and from the m-stage delay circuits and n×

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