Digital matched filter

Details Digital matched filter Digital matched filter

1998-11-19

2001-01-30

Bocure, Tesfaldet (Department: 2731)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S343000

Reexamination Certificate

active

06181733

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a digital matched filter, and more particularly to a digital matched filter suitable for use as a correlation detector which performs correlation detection of a spectrum spread signal in a portable telephone or the like.
BACKGROUND ART
In a spectrum spread communication based on a code division multiplex access (CDMA) system which has been studied for use in the portable telephone or the like, a matched filter is used when a spectrum spread signal is demodulated to an original narrow-band signal (for example, “LSI, 110 mw for Digital Portable Telephone CDMA and Reduction of Consumption Power”, Nikkei Electronics, No. 656, pp. 14-15, February, 1996).
FIG. 1
is a block diagram showing a conventional example of an eight-times spread 8-order digital matched filter constructed by using a FIR digital filter (for example, “Spectrum Spread Handbook Edition No. 4”, Stanford Telecom Inc., 1996). A transfer function H(z) of this digital matched filter is expressed by the following equation.
H
(
z
)=
C
0
+C
1
Z
−1
+C
2
Z
−2
+C
3
Z
−3
++C
4
Z
−4
+C
5
Z
−5
+C
6
Z
−6
+C
7
Z
−7
  (1)
This digital matched filter comprises a signal input terminal
1
, a clock input terminal
2
, a tapped shift register
10
including first to seventh flip-flop sets
11
-
17
, first to eighth multipliers
21
-
28
, first to seventh adders
31
-
37
, and an output terminal
5
. Here, each of the first to seventh flip-flop sets
11
-
17
constituting the tapped shift register
10
includes 6 flip-flops connected in parallel to each other.
A digital signal I
o
generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal
1
. The digital signal I
o
is a 6-bit digital signal in terms of two's complement that is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal
2
. The digital signal I
o
is applied to the first flip-flop set
11
of the tapped shift register
10
, and then is sequentially shifted from the first flip-flop set
11
toward the seventh flip-flop set
17
in synchronism with the clock CLK.
Each of the first to eighth multipliers
21
-
28
is a multiplier for 6 bits×1 bit, and outputs an output signal of 6 bits. In the first multiplier
21
, multiplication of the digital signal I
o
(6 bits) by a despreading code C
0
(1 bit) of an 8-bit despreading code sequence C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
o
is carried out. In the second to eighth multipliers
22
-
28
, multiplication operations of output signals of the first to seventh flip-flop sets
11
-
17
by the despreading codes C
1
-C
7
are carried out, respectively.
For example, when the despreading code indicates “0”, the multiplication operations of the digital signal I
o
and the output signals of the first to seventh flip-flop sets
11
-
17
by “−1” are carried out in the multipliers
21
-
28
, respectively. When the despreading code indicates “1”, the multiplication operations of the digital signal I
o
and the output signals of the first to seventh flip-flop sets
11
-
17
by “1” are carried out, respectively. The method of the multiplication operations in the multipliers
21
-
28
is not limited to this. For example, when the despreading code indicates “0”, the multiplication operations of the digital signal I
o
and the output signals of the first to seventh flip-flop sets
11
-
17
by “1” may be carried out, respectively. When the despreading code indicates “1”, the multiplication operations of the digital signal I
o
and the output signals of the first to seventh flip-flops
11
-
17
by “−1” may be carried out, respectively.
The procedure for the multiplication in each of the multipliers
21
-
28
will be described hereunder with reference to FIG.
2
.
In the initial state, all of the output signals of the first to seventh flip-flop sets
11
-
17
constituting the tapped shift register
10
are rendered to be “0”.
In the first operation state, a first sampling data D
0
of the digital signal I
o
is inputted to the signal input terminal
1
, and then the multiplication of the sampling data D
0
by the despreading code C
0
is carried out in the first multiplier
21
. Accordingly, an output signal indicative of a value of D
0
×C
0
is outputted from the first multiplier
21
.
In the second operation state, a second sampling data D
1
of the digital signal I
o
is inputted to the signal input terminal
1
in synchronism with the clock CLK, and the first sampling data D
0
is fetched in the first flip-flop set
11
. As a result, the multiplication of the second sampling data DI by the despreading code C
0
is carried out in the first multiplier
21
, and the multiplication of the first sampling data D
0
by the despreading code C
1
is carried out in the second multiplier
22
. Accordingly, an output signal indicative of a value of D
1
×C
0
is outputted from the first multiplier
21
, and an output signal indicative of a value of D
0
×C
1
is outputted from the second multiplier
22
.
In the third operation state, a third sampling data D
2
of the digital signal I
o
is inputted to the signal input terminal
1
in synchronism with the clock CLK, the first sampling data D
0
is fetched in the second flip-flop set
12
, and the second sampling data D
1
is fetched in the first flip-flop set
11
. As a result, the multiplication of the third sampling data D
2
by the despreading code C
0
is carried out in the first multiplier
21
, the multiplication of the second sampling data D
1
by the despreading code C
1
is carried out in the second multiplier
22
, and the multiplication of the first sampling data D
0
by the despreading code C
2
is carried out in the third multiplier
23
. Accordingly, an output signal indicative of a value of D
2
×C
0
is outputted from the first multiplier
21
, an output signal indicative of a value of D
1
×C
1
is outputted from the second multiplier
22
, and an output signal indicative of a value of D
0
×C
2
is outputted from the third multiplier
23
. Subsequently, a similar operation is repeated until a seventh operation state.
In the eighth operation state, an eighth sampling data D
7
of the digital signal I
o
is inputted to the signal input terminal
1
in synchronism with the clock CLK, and the first to seventh sampling data D
0
-D
6
are fetched in the seventh to first flip-flop sets
17
-
11
, respectively. Accordingly, an output signal indicative of a value of D
7
×C
0
is outputted from the first multiplier
21
, an output signal indicative of a value of D
6
×C
1
is outputted from the second multiplier
22
, an output signal indicative of a value of D
5
×C
2
is outputted from the third multiplier
23
, an output signal indicative of a value of D
4
×C
3
is outputted from the fourth multiplier
24
, an output signal indicative of a value of D
3
×C
4
is outputted from the fifth multiplier
25
, an output signal indicative of a value of D
2
×Cs is outputted from the sixth multiplier
26
, an output signal indicative of a value of D
1
×C
6
is outputted from the seventh multiplier
27
, and an output signal indicative of a value of D
0
×C
7
is outputted from the eighth multiplier
28
.
Through the above operation, the multiplication operations necessary to determine a correlation value between the initial 8 sampling data D
0
-D
7
of the digital signal I
o
and the 8-bit despreading code sequence C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
are all carried out.
In the ninth operation state, a ninth sampling data D
8
of the digital signal I
o
is inputted to the signal input terminal
1
in synchronism with the clock CLK, and the second to eighth sampling data D
1
-D
7
are fetched in the seventh to first flip-flop sets
17
-
11
, respectively. Accordingly, an output signal indicative of a value of D
8
×C
0
is outputted f

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