Digital loop synchronization circuit

Details Digital loop synchronization circuit Digital loop synchronization circuit

1979-07-31

1981-12-15

Stewart, David L.

Multiplex communications

Wide area network

Packet switching

370 79, 370 86, H04J 306

Patent

active

043063047

ABSTRACT:
There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to add or subtract delay as necessary. A FIFO register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the FIFO register. If a unique frame bit is not received in the anticipated position the output FIFO clock skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.

REFERENCES:
patent: 3681759 (1972-08-01), Hill
patent: 3919484 (1975-11-01), Maxemchur
patent: 4071706 (1978-01-01), Warren
patent: 4158748 (1979-06-01), En

Affiliated with

Also associated with

Rating

Digital loop synchronization circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital loop synchronization circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital loop synchronization circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1907170