Digital loop carrier system having multiplexed interrupt structu

Details Digital loop carrier system having multiplexed interrupt structu Digital loop carrier system having multiplexed interrupt structu

1988-08-31

1989-11-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 80, H04J 316

Patent

active

048812250

ABSTRACT:
A system having a plurality of channel units for connection to a transmission line having a plurality of timeslots. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing. An active channel unit has the ability to request communication with the processor by an interrupt signal.

REFERENCES:
patent: 3692942 (1972-09-01), Inose et al.
patent: 4760573 (1988-07-01), Calvignac et al.
patent: 4763320 (1988-08-01), Rudolph et al.
patent: 4785450 (1988-11-01), Bolgiano et al.
patent: 4791629 (1988-12-01), Burns et al.

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