Digital logic wire delay simulation

Details Digital logic wire delay simulation Digital logic wire delay simulation

1994-11-30

1997-08-05

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 9455

Patent

active

056551070

ABSTRACT:
A digital logic simulation system simulates a digital logic system having component blocks connected by nets with a master queue that contains events to be performed during the simulation, a scheduler that adds events to the master queue such that the processing of each block is represented by an update event and a compute event, and a dispatcher that maintains a time clock that defines a simulation clock time, extracts events from the master queue according to the simulation clock time, and produces a simulation output, such that wire delays for particular nets are modelled with a corresponding update event and compute event. Only those nets that have an associated wire delay that is being modelled will cause a wire delay update event and compute event. All other nets will not result in wire delay events.

REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5572437 (1996-11-01), Rostoker et al.

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