Digital logic protocol interface for different semiconductor tec

Details Digital logic protocol interface for different semiconductor tec Digital logic protocol interface for different semiconductor tec

1992-01-23

1994-03-29

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, H03K 190175

Patent

active

052988082

ABSTRACT:
A method and apparatus for implementing silicon logic interface protocols in compound semiconductor technology converts the voltages corresponding to standard logic digital values to voltages appropriate to these digital values in compound semiconductor technology, and vice versa. In an input buffer circuit of the present invention, the voltage of the converted logic level depends only on the difference between the input standard voltage level and a reference voltage which corresponds to the threshold voltage of silicon logic so that the converted voltage is independent of device process, circuit temperature, and power supply output variations to first order. A source follower input is used so that the driving logic circuit need not source current to or sink current from the input buffer circuit so that fanout is not limited. An output buffer circuit of the present invention achieves a stable output buffer tri-state functionality and eliminates leakage current problems by a modification of a standard totem pole output configuration. A standard totem pole type output is modified to use a second pull-down MESFET which puts the source of the first pull-down MESFET at a small positive voltage. As a result, the gate-source diode of the first pull-down MESFET is reverse biased, shutting the first pull-down MESFET off hard.

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Srivastava, A. K. "Gallium ARisenide" IEEE Potentials, Oct. 1989 pp. 23-25 Vitesse Semiconductor Corporation data sheet dated Feb., 1990.

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