Digital logic level signal indication of phase and frequency loc

Details Digital logic level signal indication of phase and frequency loc Digital logic level signal indication of phase and frequency loc

1977-10-21

1978-10-24

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307232, 328133, 331 25, 331 64, H03D 304, H03K 520

Patent

active

041224051

ABSTRACT:
A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.

REFERENCES:
patent: 3982190 (1976-09-01), Schaefer
Hill, "Out of Lock Detector for Automatic Phase Control," Electronic Design, Nov. 8, 1965, pp. 53-54.
Leck, "Logic Gates and LED Indicate Phase Lock," Electronics, vol. 48, No. 11, May 29, 1975, p. 106.

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