Digital logic circuits for frequency multiplication

Details Digital logic circuits for frequency multiplication Digital logic circuits for frequency multiplication

1990-09-24

1991-11-05

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 76, 377118, H03K 2108, H03K 2300, H03B 1900

Patent

active

050635786

ABSTRACT:
A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12, 13 in A1, A2, A3, . . . and B1, B2, B3, . . . ). Further, the n'th one of set of clocked latches (14, 15, 16 in A2, A4, A6, . . . ) derives its input from the 2n'th one of the delay elements in the first chain, where n is a running integer index (n=1,2,3, . . . ). The circuit (100) also includes a set of two-input logic gates (11), one of whose inputs (IN) is the output (OU) of a separate one of the logic elements (12, 13) in the second chain and the other of whose inputs is an output (MO) of a separate one of the latches (14, 15, 16). Each of the outputs of these logic gates (11) is fed to a multiple input output logic gate (25) whose output has a desired double-frequency feature (edges at T/4) relative to the frequency of the clocked pulse sequence (CLK).

REFERENCES:
patent: 4011516 (1977-03-01), Heimbigner et al.
patent: 4350952 (1982-09-01), Holt et al.
patent: 4780896 (1988-10-01), Dotter
patent: 4876704 (1989-10-01), Uzaki
Gutierrez, G. et al., "An Integrated PLL Clock Generator for 275 MHz Graphic Displays", IEEE 1990 Custom Integrated Circuits Conference, pp. 15.1.1-15.1.3 (1990).

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