Digital lock detect for dithering phase lock loops

Details Digital lock detect for dithering phase lock loops Digital lock detect for dithering phase lock loops

2002-09-12

2003-12-30

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000

Reexamination Certificate

active

06670834

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits generally and, more particularly, to a method and/or architecture for implementing a digital lock detect for dithering phase lock loops.
BACKGROUND OF THE INVENTION
Conventional Phase Lock Loops (PLLs) are a common implementation in many circuit designs. Phase lock loops operate as frequency scaling devices that typically generate an output signal that has a frequency that is a multiple of the frequency of an input signal.
Conventional systems implement a lock detect circuit to determine when the phase lock loop obtains a lock to either a logic high level or a logic low level. In conventional phase lock loops, the lock detect circuit monitors the stable filter voltage or checks to see that the reference signal REF and the feedback signal FB are matched in phase and/or frequency. However, in the case of a dithering PLL, the dithering action causes a constantly changing filter voltage and a constantly changing frequency/phase relationship.
Conventional approaches for dithering phase lock loops apply the filter voltage and/or the reference signal or feedback signal matching method by creating large tolerances that can absorb the modulation created by the dithering. However, such conventional approaches do not check whether the system is actually dithering as expected.
It would be desirable to have a lock detect for a dithering phase lock loop that operates reliably and checks to ensure that the system is actually dithering as expected.
SUMMARY OF THE INVENTION
The present invention concerns a first circuit and a second circuit. The first circuit may be configured to generate a first intermediate signal, a second intermediate signal, and a third intermediate signal in response to a first control signal, a second control signal, a third control signal, a reference signal and an output clock signal. The second circuit may be configured to generate an output signal in response to the first intermediate signal, the second intermediate signal, and the third intermediate signal. The output signal may indicate a lock condition between a feedback signal and the reference signal.
The objects, features and advantages of the present invention include implementing a digital lock detect for dithering phase lock loops that may (i) determine a lock condition by evaluating a number of points where an offset value has a maximum positive or negative value; and/or (ii) check and/or ensure that the system is actually dithering as expected.


REFERENCES:
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patent: 5394444 (1995-02-01), Silvey et al.
patent: 5969576 (1999-10-01), Trodden
patent: 6177842 (2001-01-01), Ahn et al.
patent: 6466058 (2002-10-01), Goldman
patent: 6522206 (2003-02-01), Kornblum et al.

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