Digital linear voltage regulator

Details Digital linear voltage regulator Digital linear voltage regulator

2011-04-05

2011-04-05

Nguyen, Matthew V (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

07919957

ABSTRACT:
A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

REFERENCES:
patent: 6031362 (2000-02-01), Bradley
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patent: 7283784 (2007-10-01), Smith et al.
patent: 2007/0290894 (2007-12-01), Ng et al.
Gabriel, Active Capacitor Multiplier in Miller-Compensated Circuits, IEEE Transactions on Solid-State Circuits, vol. 35, No. !, Jan. 2000.
Hazucha et al., Area-Efficient Linear Regulator, With Ultra-Fast Load Regulation. IEEE Journal of Solid-State Circuits, vol. 40, No. 4, Apr. 2005.

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