Digital limiter

Details Digital limiter Digital limiter

1984-08-27

1986-09-16

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307540, 328172, 333 81R, H03K 508, H03G 1100

Patent

active

046125078

ABSTRACT:
A soft digital limiter (2) for limiting an analog input signal (1) from a maximum expected range (61) to a useful range (60). The number (m) of desired levels of resolution in the limiter (2) is preselected to be any power of two. An analog-to-digital converter (9) converts the input analog signal (1) to a digital representation (20). The converter (9) has its input voltage rating matched to the maximum expected range (61) and its output resolution matched to the preselected degree (m) of resolution. In the preferred two's complement numbering system, the condition for the input signal (1) falling within the useful range (60) is that the most significant p+1 bits of the digital representation (20) are all identical, where p is the number of bits required by the converter (9) to delineate that portion of the maximum expected range (61) outside of the useful range (60). A network of comparators (e.g., 38, 39) implements this condition.

REFERENCES:
patent: 3883817 (1975-05-01), Cliff
patent: 3930256 (1975-12-01), Amemiya
patent: 4191995 (1980-03-01), Farrow
patent: 4263565 (1981-04-01), Astle
patent: 4412299 (1983-10-01), Huffman
Linear Integrated Circuits, RCA (1982), pp. 316, 322, "CMOS Video Speed 6-Bit Flash Analog-to-Digital Converter".
Signetics TTL catalogue, (1983), p. 4-241, Logic Products.

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