Digital lattice filter with multiplexed full adder

Details Digital lattice filter with multiplexed full adder Digital lattice filter with multiplexed full adder

1984-08-31

1987-10-13

Malzahn, David H.

Boots, shoes, and leggings

381 51, G06F 1531, G10L 100

Patent

active

047003235

ABSTRACT:
A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit. The addition operation is performed on the generated product by circulating the product back to the B-input of the adder (44) through the multiplexer (66). Data is selected from the output of a data stack (52) or from a D-register (108) which contains a prestored output value.

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patent: 4597053 (1986-06-01), Chamberlin

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