Digital integrator with reduced circuit area and analog-to-digit

Details Digital integrator with reduced circuit area and analog-to-digit Digital integrator with reduced circuit area and analog-to-digit

1993-02-16

1994-07-05

Young, Brian K.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

341166, H03M 150

Patent

active

053271335

ABSTRACT:
A digital integrator (22) reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder (51). In the z-domain, he transfer function of a two-stage integrator can be expressed as H(z)=(1/(1-z.sup.-1)).sup.2. Expanded, the transfer function is expressed as H(z)=(1/(1 -2z.sup.-1 +z.sup.-2)). The inverse z-transform yields the expression y[n]=x[n]+2y[n-1]-y[n-2], which can be implemented with a single adder (51) and two delay portions (52, 55 and 53, 54). In one embodiment, a three-stage integrator (22) can further be implemented within a single adder circuit (91) by time-multiplexing an addition required for the two-stage integration with an addition required for a one-stage integration inside the adder circuit (91).

REFERENCES:
patent: 4736242 (1988-04-01), Takanashi et al.
patent: 4972356 (1990-11-01), Williams
patent: 4999798 (1991-03-01), McCaslin
patent: 5084702 (1992-01-01), Ribner
patent: 5103229 (1992-04-01), Ribner

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