1986-07-07
1988-03-08
Smith, Jerry
Excavating
371 15, 324 73R, G01R 3128
Patent
active
047303174
ABSTRACT:
A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.
REFERENCES:
patent: 4317200 (1982-02-01), Wakatsuki
patent: 4567593 (1986-01-01), Bashaw
patent: 4575674 (1986-03-01), Bass
patent: 4597042 (1986-06-01), d'Angeac
patent: 4635261 (1987-01-01), Anderson
Desyllas Peter L. L.
Naven Finbar
Beausoliel Robert W.
International Computers Limited
Smith Jerry
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