Digital integrated circuit with multi-mode register

Details Digital integrated circuit with multi-mode register Digital integrated circuit with multi-mode register

1986-03-17

1987-10-20

Atkinson, Charles E.

Excavating

324 73R, 371 25, G01R 3128

Patent

active

047019166

ABSTRACT:
A digital integrated circuit comprises a number of registers each of which comprises several data bits and at least one control bit cell. In a normal operation state, all the registers act as parallel input/output registers. In a SHIFT state, the data bits and control bit cells of all the registers are linked together to from a serial shift path between a pair of external terminals allowing test data to be shifted in or out as required. In a TEST state, each register is set into one of a number of test modes, controlled by the test bit cells of that register. The test modes include a test generate mode in which the register acts as a pseudo-random number generator, and a test analyze mode in which it acts as a digital signature analyzer.

REFERENCES:
patent: 4317200 (1982-02-01), Wakatsuki et al.
patent: 4476431 (1984-10-01), Blum
patent: 4498172 (1985-02-01), Bhavsar
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komorytsky
patent: 4534028 (1985-08-01), Trischler
patent: 4567593 (1986-01-01), Bashaw
patent: 4635261 (1987-01-01), Anderson et al.
Konemann et al., Built-in Test for Complex Digital Integrated Circuits, Fifth European Solid State Circuits Conference, ESSCIRC 79, Southampton, England, (Sep. 18-29, 1979) pp. 89-90.
Bhavsar et al., Self-Testing by Polynomial Division, Digest of Papers, 1981 Intl. Test Conference, IEEE, pp. 208-216.

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