Digital integrated circuit comprising complementary field effect

Details Digital integrated circuit comprising complementary field effect Digital integrated circuit comprising complementary field effect

1984-04-13

1987-05-19

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

046673032

ABSTRACT:
Digital integrated C-MOS circuit in which two cross-coupled P-MOS transistors are connected by two separation transistors (N-MOS) to two complementary switching N-MOS transistor logic networks. The gate electrodes of the separation transistor are connected to a reference voltage source. The switching speed of the C-MOS circuit is increased in that (a) the voltage sweep across the logic networks is reduced; (b) each P-MOS transistor, which is connected by a separation transistor to a junction of the logic network to be charged, is slightly conducting and so is "ready" to charge such junction, and (c) the separation transistor between the fully conducting P-MOS transistor and the junction to be discharged in the second logic network constitutes a high impedance which prevents the conducting P-MOS transistor from charging that junction.

REFERENCES:
patent: 3878986 (1975-04-01), Hirasawa
patent: 4042841 (1977-08-01), Hills et al.
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4471454 (1984-09-01), Dearden et al.

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