Boots – shoes – and leggings
Patent
1980-04-28
1983-02-22
Springborn, Harvey E.
Boots, shoes, and leggings
377 55, G06F 1100, G06M 302
Patent
active
043750842
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a digital input apparatus and in particular to a digital input apparatus which can eliminate chattering caused by the opening or closing of a contact and noise components caused by electromagnetic induction.
BACKGROUND OF THE PRIOR ART
FIG. 1 shows a conventional digital input apparatus.
A plurality of input signals 11, 12, 13, 14 and 15 are supplied through a multiplexer 16 to a signal processing apparatus such as a computer and in order to prevent chattering, a filter circuit 21 comprising resistors 17, 18, capacitor 19 and inverter 20 is used in the conventional apparatus. Since in the CR filter including the capacitor 19 and resistors 17, 18 there is a variation in the values of the elements, a variation in delay time occurs. In order to correct such a variation, a more complicated correction circuit is necessary, leading to an increase in discrete parts. As a filter circuit is required for each input signal, if the number of input signals is increased, the number of discrete parts is increased, leading to a complicated circuit, difficulty in assembly and a rise in cost.
FIG. 2 shows a digital input apparatus having a status variation detection function as in the prior art. In FIG. 2, respective input signals 22, 23, 24, 25 are supplied respectively through filter circuits 26 to a multiplexer 27 and corresponding status detection circuits 28. The status detection circuits 28 are each constructed of a differential circuit. The output signals of the status detection circuits 28 are supplied to an OR circuit 29. The output signal of the OR circuit 29 is supplied to an interrupt circuit 30. When an input signal varies in the digital input apparatus, one or a plurality of detection pulses are produced from the status detection circuit 28. The detection pulse is supplied through the OR circuit 29 to the interrupt circuit 30. The interrupt circuit 30 interrupts a computer which in turn receives an output signal which is outputted by an interrupt operation from the multiplexer 27.
Since in such a conventional system a the filter circuit 26 and status detection circuit 28 are required for each input signal the number of discrete parts is increased in proportion to an increase in the number of input signals, resulting in a lower packing density and in an expensive digital input apparatus.
It is accordingly an object of this invention to provide a high-reliability digital input apparatus free from the above-mentioned drawbacks, in which even if noise resulting from chattering etc. is superposed onto an input signal, the input signal is digitally processed to permit the delay time of the input signal to be equalized.
SUMMARY OF THE INVENTION
This invention provides a digital input apparatus which requires fewer component parts, in which a flip-flop and counter are provided so as to obtain a filter effect, and a delay time can be easily and accurately set by varying the cycle of clock signals and bit length of the counter.
The counter is used on a time sharing basis and even if the number of input signals is increased the number of component parts is not correspondingly increased. Further, an improvement in manufacturability as well as in packing density can be attained without using discrete parts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing one form of a conventional digital input apparatus;
FIG. 2 is a circuit diagram showing another form of a conventional digital input apparatus;
FIG. 3 is a block diagram showing a multiplexed digital input apparatus according to an embodiment of this invention;
FIGS. 4A-4F show pulse waveforms of address signals from a timing generator and timing signals from a decoder of the digital input apparatus of FIGS. 3 and 9, as indicated below;
FIG. 4A shows a pulse waveform of an address signal a;
FIG. 4B shows a pulse waveform of an address signal b;
FIG. 4C shows a pulse waveform of an address signal c;
FIG. 4D shows a pulse waveform of an address signal d;
FIG. 4E shows a pulse waveform of an addr
REFERENCES:
patent: 3331060 (1967-07-01), Willis
patent: 3891971 (1975-06-01), Hirvela et al.
patent: 4106091 (1978-08-01), Hepworth
Springborn Harvey E.
Tokyo Shibaura Denki Kabushiki Kaisha
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