Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1999-11-01
2003-06-03
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C386S349000
Reexamination Certificate
active
06574290
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a digital information reproducing apparatus such as a magnetic disk apparatus or the like and relates to a reproducing method.
2. Description of the Related Art
In recent years, a maximum likelihood decoding system has frequently been used as a signal processing system which enables a high density recording. According to the maximum likelihood decoding system, maximum likelihood data is decoded at each time point while an amplitude level of a reproduction signal at a previous time point is referred to. If it has been known that the reproduction signal changes under some restriction, by knowing information regarding the reproduction signal at the previous time point, the decoding of higher precision than that in case of decoding by a bit-by-bit system can be performed.
In a PRML (Partial Response Maximum Likelihood) system which is a typical maximum likelihood decoding system and is constructed by a combination of a Viterbi decoding method and Partial Response, problems in the maximum likelihood decoding system will now be described hereinbelow with respect to PR
1
ML using, particularly, Partial Response Class
1
(hereinbelow, referred to as PR
1
) as an example.
An equalization signal which is obtained by PR
1
equalization is also called PR(1,1). When “
1
” is inputted, an intercode interference of “1” occurs in the next bit. Therefore, two statuses (S
0
, S
1
) are determined in dependence on whether the just previous input value is equal to “0” or “1”. An output value is, further, decided by the next input value in each of those statuses and the status is shifted to the next status.
FIG. 10
shows an example of a rule of such a status transition.
FIG. 11
is a trellis diagram showing a state of a status transition which can occur for one time point.
As a specific process to decide the status transition on the basis of the reproduction signal, the square of a difference between a reproduction signal level and a reference amplitude level (expected value) is calculated as follows at each time k. Calculation values which are obtained by such a method are referred to as branch metrics.
BM
10
=(
Z
(
k
)−1)
2
(1)
BM
11
=(
Z
(
k
)−2)
2
(2)
BM
00
=(
Z
(
k
)−0)
2
(3)
BM
01
=(
Z
(
k
)−1)
2
(4)
The equation (1) denotes a probability with respect to an assumption that the status S
1
is shifted to the status S
0
. The equation (2) denotes a probability with respect to an assumption that the status S
1
is shifted to the status S
1
. The equation (3) denotes a probability with respect to an assumption that the status S
0
is shifted to the status S
0
. The equation (4) denotes a probability with respect to an assumption that the status S
0
is shifted to the status S
1
.
As mentioned above, according to the maximum likelihood decoding system, maximum likelihood data is decoded at each time point while the amplitude level of the reproduction signal at the previous time point is referred to. For this purpose, the sum of the branch metrics until the status reaches the status S
0
or S
1
at each time point is stored. The sum of the branch metrics is called a path metric. In the actual decoding process, the value of the path metric is updated at each time k in accordance with the following calculations.
MT
0
k
=min(
MT
0
k−1
+BM
00
,
MT
1
k−1
+BM
10
) (5)
MT
1
k
=min(
MT
0
k−1
+BM
01
,
MT
1
k−1
+BM
11
) (6)
where, MT
0
k
denotes a path metric of the status S
0
at time k and MT
0
k−1
denotes a path metric of the status S
0
at time k−1. Similarly, MT
1
k
denotes a path metric of the status S
1
at time k and MT
1
k−1
denotes a path metric of the status S
1
at time k−1.
An arithmetic operating process according to the equation (5) is an operation for calculating probabilities of the path reaching S
0
from S
0
and the path reaching S
0
from S
1
for an interval from time k−1 to time k and leaving the more probable path. An arithmetic operating process according to the equation (6) is an operation for calculating probabilities of the path reaching S
1
from S
0
and the path reaching S
1
from S
1
for an interval from time k−1 to time k and leaving the more probable path.
At time k, when the path reaching S
0
from S
0
is selected by the arithmetic operating process according to the equation (5) and the path reaching S
1
from S
0
is selected by the arithmetic operating process according to the equation (6), it is determined that the status at time k−1 is S
0
and the statuses (paths) at all times before time k−1 are determined. An example of the paths which are determined in this manner is shown by bold lines in FIG.
12
.
FIG. 12
shows an example of trellis diagrams among a plurality of time points.
A decoding apparatus for performing a maximum likelihood decoding has a construction to realize the foregoing processes. That is, the decoding apparatus has: a branch metric calculating circuit for calculating values of branch metrics in accordance with the equations (1) to (4); an ACS (Add Compare select) circuit for calculating the sum of a branch metric which is newly calculated at time k and the path metrics calculated until time k−1 in accordance with the equations (5) and (6) and selecting the more probable path on the basis of a calculation value; and a path memory circuit for storing a value of the path metric at time point k−1 which is used in the arithmetic operating process by the ACS at each time point k.
The ACS circuit will now be described in more detail hereinbelow in order to explain the problems in the maximum likelihood decoding.
FIG. 13
shows an example of the ACS circuit. Two ACS circuits
100
and
200
perform the arithmetic operating processes according to the equations (5) and (6), respectively. In the arithmetic operating processes, an adding process, a comparing process, and a selecting process have to be performed as a series of processes for a period of time of one clock. In the ACS circuits
100
and
200
, therefore, pipeline processes cannot be performed, it is also extremely difficult to perform parallel processes, and this results in a large obstacle in realization of a high processing speed of the Viterbi decoder.
As a recording modulating system, a (1,7) RLL (Run Length Limited) code in which: the number of “0” between “1” and “1” is limited to 1 or more and 7 or less, a (2, 7) RLL code in which the number of “0” between “1” and “1” is limited to 2 or more and 7 or less, or the like is known. According to those codes, since a shortest inverting interval T
min
is large, they are suitable for short wavelength recording. However, a clock rate rises (1.5 times, 2 times, respectively). Therefore, the combination of those recording modulating systems and the maximum likelihood decoding are improper to perform the recording and/or reproduction at a high speed.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the invention to provide a digital information reproducing apparatus and a reproducing method which can solve the problems in the conventional techniques and perform the maximum likelihood decoding at a high speed.
According to one aspect of the invention, there is provided a digital information reproducing apparatus in which a digital reproduction signal that is reproduced from a recording media, and that is constructed by collecting Partial Response encoded signal portions each having a predetermined data amount is decoded by maximum likelihood decoding, comprising:
equalizing means for equalizing the digital reproduction signal by predetermined equalizing characteristics;
clock forming means for forming a first clock signal on the basis of an output of the equalizing means;
A/D converting means for A/D (analog/digital) converting the digital reproduction signal by the first clock signal;
time base decompressing means fo
Chin Stephen
Frommer William S.
Frommer & Lawrence & Haug LLP
Savit Glenn F.
Sony Corporation
LandOfFree
Digital information reproducing apparatus and reproducing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital information reproducing apparatus and reproducing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital information reproducing apparatus and reproducing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3113449