Digital in-circuit tester having channel-memory earse-preventer

Details Digital in-circuit tester having channel-memory earse-preventer Digital in-circuit tester having channel-memory earse-preventer

1987-05-29

1989-08-08

Lall, Parshotam S.

Excavating

324 73R, 364900, G01R 3128

Patent

active

048560014

ABSTRACT:
A digital in-circuit tester has a test-head controller which controls bursts of test vectors generated by a group of driver-receiver channels, the group of driver-receiver channels responsive to an erase instruction from test-head controller. At least one driver-receiver channel is adapted for nullifying the action of an erase instruction. The driver-receiver channel has a first memory for storing information which determines certain actions of the channel during the next burst of test vectors. The memory is responsive to the erase instruction for being erased. The driver-receiver channel also has an erase inhibitor including: an inhibition-state-retention means responsive to an erase-inhibit instruction from the test-head controller for storing an erase-inhibit logic state; and a combinatorial means communicatively coupled to the inhibition-state-retention means, and responsive to the stored erase-inhibit logic state from the inhibition-state-retention means, and responsive to the test-head controller erase instruction for nullifying the action of the erase instruction.

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