Digital implementation of power factor correction

Details Digital implementation of power factor correction Digital implementation of power factor correction

2008-04-15

2008-04-15

Sterrett, Jeffrey (Department: 2838)

Electric power conversion systems

Current conversion

With condition responsive means to control the output...

Reexamination Certificate

active

07359224

ABSTRACT:
A circuit for providing power factor correction in accordance with an embodiment of the present application may include a boost converter circuit and a control circuit receiving as inputs a rectified AC input voltage from a rectifier, a signal proportional to current through the boost inductor and the DC bus voltage across the capacitor of the boost converter. The control circuit provides a pulse width modulated signal to control the on time of a PFC switch. The control circuit further includes a voltage regulator and a current regulator. The current regulator includes a difference device operable to subtract a signal proportional to the inductor current from the current reference signal, a PI controller adapted to receive the output of the difference device and provide a first control signal, a feed forward device operable to receive the rectified AC input voltage and to provide a second control signal with a smaller dynamic range than the AC input voltage, and an adder operable to add the first control signal to the second control signal to provide a PWM reference signal for generating the pulse width modulated signal. A zero crossing detector and vector rotator may be provided to provide a clean sinusoidal reference to the current regulator. A partial PFC regulator may be provide to provide partial mode PFC if desired.

REFERENCES:
patent: 5003454 (1991-03-01), Bruning
patent: 5638265 (1997-06-01), Gabor
patent: 5801935 (1998-09-01), Sugden et al.
patent: 6215287 (2001-04-01), Matsushiro et al.
patent: 6320772 (2001-11-01), Doyama et al.
patent: 6728121 (2004-04-01), Ben-Yaakov et al.
patent: 6738274 (2004-05-01), Prasad et al.
patent: 7042743 (2006-05-01), Pidutti et al.
patent: 7088081 (2006-08-01), Takahashi et al.
patent: 7164591 (2007-01-01), Soldano
patent: 7183753 (2007-02-01), Tsuruya
patent: 7239120 (2007-07-01), Adragna et al.
patent: 7257010 (2007-08-01), Takahashi
patent: 2005/0270813 (2005-12-01), Zhang et al.
patent: 2006/0013026 (2006-01-01), Frank et al.
patent: 2006/0245219 (2006-11-01), Li
International Search Report dated Oct. 10, 2006.

Affiliated with

Also associated with

Rating

Digital implementation of power factor correction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital implementation of power factor correction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital implementation of power factor correction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2772775