Digital image processing apparatus for correctly addressing imag

Details Digital image processing apparatus for correctly addressing imag Digital image processing apparatus for correctly addressing imag

1988-09-26

1991-06-04

Razavi, Michael

Image analysis

Histogram processing

For setting a threshold

382 50, 358448, G06K 900

Patent

active

050220900

ABSTRACT:
Each of the processing circuits connected to an image data bus is adapted such that a delay of n transfer clocks (n is a positive integer) or an integer multiple thereof is generated between the input and output data. Therefore, the delay time of the whole processing circuit becomes an integer multiple of a fixed time period, no matter what pipeline structure is adopted to connect the processing circuits. An address counter connected to the image memory through an address bus delays one read address by a plurality of cascade connected delay circuits and outputs the same as write address with the output of respective delay circuit switched successively, so that it seemingly operates in the same manner as in the case where there are a number of write address counters.

REFERENCES:
patent: 4464789 (1984-08-01), Sternberg
patent: 4574394 (1986-03-01), Holsztynski et al.
patent: 4665551 (1987-05-01), Sternberg et al.
patent: 4665554 (1987-05-01), Sternberg
patent: 4860375 (1989-08-01), McCubbrey et al.

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