Digital I/O bus controller circuit with auto-incrementing, auto-

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395824, 395835, 395837, 395866, G06F 1320

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active

055242677

ABSTRACT:
A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of "polling" a device's internal register by accessing the polling function.

REFERENCES:
patent: 4177512 (1979-12-01), Moggia
patent: 5150328 (1992-09-01), Aichelmann, Jr.
patent: 5166903 (1992-11-01), Aichelmann, Jr.
patent: 5187795 (1993-02-01), Balmforth et al.
patent: 5214760 (1993-05-01), Hammond et al.
patent: 5235689 (1993-08-01), Baker et al.

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