Digital hardware architecture for realizing neural network

Details Digital hardware architecture for realizing neural network Digital hardware architecture for realizing neural network

1997-02-27

1998-09-22

MacDonald, Allen R.

Data processing: artificial intelligence

Neural network

Structure

706 15, 706 25, 706 27, 706 41, 706 43, G06F 1518, G06E 100

Patent

active

058129936

ABSTRACT:
A digital neural network architecture including a forward cascade of layers of neurons, having one input channel and one output channel, for forward processing of data examples that include many data packets. Backward cascade of layers of neurons, having one input channel and one output channel, for backward propagation learning of errors of the processed data examples. Each packet being of a given size. The forward cascade is adapted to be fed, through the input channel, with a succession of data examples and to deliver a succession of partially and fully processed data examples each consisting of a plurality of packets. The fully processed data examples are delivered through the one output channel. Each one of the layers is adapted to receive as input in its input channel a first number of data packets per time unit and to deliver as output in its output channel a second number of data packets per time unit. The forward cascade of layers is inter-connected to the backward cascade of layers by means that include inter-layer structure, such that, during processing phase of the forward cascade of neurons, any given data example that is fed from a given layer in the forward cascade to a corresponding layer in the backward cascade, through the means, is synchronized with the error of the given processed data example that is fed to the corresponding layer from a preceding layer in the backward cascade. The first number of data packets and the second number of data packets being the same for all the layers.

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