Digital frequency synthesizer having multiple processing paths

Boots – shoes – and leggings

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G06F 102

Patent

active

049583107

ABSTRACT:
A digital-to-analog converter receives buffered data words from a multiplexer having "N" inputs, each input receiving data from one of N processing paths, each path having a memory therein which provides the data. Each memory receives address information from a variable-increment counter in its path. The counters are initialized by an offset loader when a frequency is selected. The initialization is a two step process: (1) the counters are loaded with an initial value, and (2) an increment register is loaded with a number equal to N times a primary incremental value corresponding to the frequency. Initially, a first path counter is set to zero, a second path counter is offset by the incremental value, a third path counter is set to twice the incremental value, and so on until the last counter is offset by N-1 times the incremental value. Thereafter all path counters are sequentially incremented by the primary incremental value times N in order from first to last in cycles, and the data from the paths are selected by the multiplexer in the same order. The clocking of each path counter in a cycle precedes the selection of the path by a portion of the cycle sufficient to allow each path time to complete its incrementing process and have settled data at its respective multiplexer input before it is again selected.

REFERENCES:
patent: 4068178 (1978-01-01), Tuzi
patent: 4486846 (1984-12-01), McCallister et al.
patent: 4710891 (1987-12-01), Debus, Jr. et al.

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