Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
1997-10-24
2001-05-22
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S018000, C331S016000, C331S017000, C327S157000, C327S159000, C327S107000, C327S106000
Reexamination Certificate
active
06236275
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to digital frequency synthesis, and in particular, to digital frequency synthesis wherein frequencies may be changed rapidly with high resolution and minimal phase modulation.
Synthesis is the making up of a whole by combining separate parts or elements, and frequency synthesizers produce a range of output frequencies using this principle. Early frequency synthesizers used multiple crystals and contained as many crystal oscillators as frequency decades. Due to advances in various technologies, these multi-crystal synthesizers have now been superseded by single crystal synthesizers.
Direct synthesizers add and subtract multiples and submultiples of a single crystal oscillator frequency to provide a wide range of output frequencies. One such synthesizer is a multi-loop synthesizer which works on a “divide-and-add” principle. For example, if a 1 KHz output frequency is divided by 10 using a digital counter, the result is 100 Hz frequency resolution at one tenth the 1 KHz output frequency. Using a conventional heterodyne frequency converter or “mixer”, the resulting 100 Hz frequency may be added to the 1 KHz output frequency to generate successive 100 Hz steps. The 100 Hz frequency may also be divided by 10 to yield 10 Hz steps. These 10 Hz steps may then be added and/or subtracted to any of the preceding frequencies. Unfortunately, direct synthesizers suffer some serious drawbacks including generation of unwanted frequencies by the mixers requiring extensive filtering, a high sensitivity to wideband phase noise, complex circuitry, and a relatively high manufacturing cost.
The required frequency range in most current synthesizers is obtained using a variable voltage-controlled oscillator (VCO) whose output frequency is corrected by comparison with a reference frequency. This type of synthesizer is oftentimes referred to as an indirect synthesizer.
A block diagram of a known phase-locked loop (PLL) digital frequency synthesizer
10
is shown in FIG.
1
. The frequency synthesizer
10
includes a reference frequency source/oscillator
12
, a reference divider (divide-by-M)
14
, a phase error detector
16
, a loop filter
18
, a voltage-controlled oscillator (VCO)
20
, and a variable VCO divider (divide-by-N)
22
. The VCO divider
22
may comprise a digital counter that generates a series of count pulses. A VCO output signal at an output frequency F
vco
is generated by the VCO
20
and is detected by the VCO divider
22
. As those skilled in the art will readily comprehend, the output frequency F
vco
is used herein to designate a frequency which is typically changing in a predetermined manner. Thus, the output frequency F
vco
may represent one or more distinct, desired frequencies or may represent a range of desired frequencies. The VCO divider
22
counts the number of cycles of the VCO output signal and produces an output pulse after every N cycles, where N is a programmable divisor that can be varied between different count cycles. The VCO divider
22
therefore produces output pulses at a frequency of the output frequency F
vco
divided by the divisor N.
In order to synthesize multiple different frequencies from the VCO
20
, the VCO divider
22
is programmed to divide by different output divisors N whose value is variably set by a control mechanism
23
based on a desired value for the output frequency F
vco
. In a typical application, the desired value of the output frequency F
vco
may be one of many possible radio frequency (RF) channels for RF transmission or RF reception. Of course, if the variable output divisor N is equal to 1, the VCO divider
22
would output count pulses forming an output pulse train having a frequency substantially identical to the current value of the output frequency F
vco
.
The output pulse train generated by the VCO divider
22
is fed back to the phase error detector
16
for comparison with a reference frequency F
ref
. The reference frequency F
ref
is usually a fixed, accurate frequency generated by a crystal oscillator; but in some cases, it is a variable frequency derived from some other source that may include another frequency synthesizer. Since the reference frequency source
12
generates a reference frequency F
ref
that is usually higher than the desired step size between frequencies generated by the VCO
20
, the reference frequency F
ref
is transformed by the reference divider
14
into a reference pulse train having a frequency corresponding to the desired step size. The reference divider
14
divides the reference frequency F
ref
by a reference integer M. The reference integer M is selected so that the phase detector
16
is able to compare the reference pulse train and the output pulse train generated by the VCO divider
22
.
The difference/error in phase or frequency between the compared pulse trains is output as a phase error signal (typically a voltage) by the phase detector
16
. The phase error signal is filtered by the loop filter
18
to produce an output error, or control, signal. The loop filter
18
is typically a low-pass filter. The characteristics of the loop filter
18
govern how the PLL responds to changes in the phase error signal. The VCO
20
is a sinusoidal oscillator whose frequency is controlled by the output error signal. A negative value for the output error signal causes the VCO
20
to decrease the output frequency F
vco
and a positive value for the output error signal causes the VCO
20
to increase the output frequency F
vco
.
In this way, the VCO
20
may be tuned through a wide range of desired values for the output frequency F
vco
simply by varying the output error signal. By continuously comparing the output frequency F
vco
of the VCO
20
with a reference frequency F
ref
having a desired accuracy and, in response thereto, continuously correcting the output error signal, the frequency synthesizer
10
can achieve a very high accuracy. Indeed, the accuracy of the frequency synthesizer
10
can be on the order of one part per million or better, which is typically the accuracy of the reference frequency source
12
.
As mentioned above, the reference frequency F
ref
generated by the reference frequency source
12
is usually not equal to the output frequency F
vco
to which the VCO
20
is currently tuned; otherwise, the reference frequency source
12
could be used directly to generate the output frequency F
vco
. Because the reference frequency F
ref
and the desired value of the output frequency F
vco
typically differ, they must first be reduced by division to some common submultiple frequency before they can be compared. For example, suppose a desired range of the output frequency F
vco
includes a series of frequencies spaced apart by frequency steps of 25 KHz, for example, 1000.000 MHz, 1000.025 MHz, 1000.050 MHz . . . , and the reference frequency F
ref
is 12.8 MHz. The reference frequency F
ref
would need to be divided by 512 (the reference integer M equal to 512) by the reference divider
14
to generate a reference pulse train having a frequency of 25 KHz which is the spacing between the desired series of output frequencies F
vco
. For this example, the reference divider
14
may be comprised of a 9-stage binary counter (2
9
=512) to produce such a reference pulse train.
The output frequency F
vco
of the VCO
20
is divided by the variable output divisor N in the VCO divider
22
. The variable output divisor N is set to one of the numbers in the series 40000, 40001, 40002 . . . corresponding to the desired output frequency F
vco
expressed in multiples of 25 KHz, i.e., 1000.000 MHz/40000=25 KHz, 1000.025 MHz/40001=25 KHz, 1000.050 MHz/40002=25 KHz . . . If the output frequency F
vco
is at the desired value, the VCO divider
22
will generate pulses at the same 25 KHz rate as the reference divider
14
. Any difference between the frequencies of the reference pulse train and the output pulse train is detected by the phase detector
16
which generates an appropriate phase error signal, or
Coats & Bennett PLLC
Ericsson Inc.
Kinkead Arnold
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