Digital frequency multiplying circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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327121, 327122, H03B 1900

Patent

active

06118313&

ABSTRACT:
A digital frequency-doubling circuit includes a pair of cascaded first delay circuits, each including a plurality of cascaded delays, and a first stage of the cascaded first delay circuits receiving an input signal to be frequency-doubled, and an exclusive-OR circuit receiving the input signal and a delayed output signal outputted from the first stage of the cascaded first delay circuits, for generating a frequency-doubled signal. A delay amount comparator receives a first delayed output signal outputted from a second stage of the cascaded first delay circuits and a second delayed output signal outputted from a second delay circuit of a small delay receiving the first delayed output signal, for performing comparison at a transition timing of the input signal, to discriminate whether the obtained frequency-doubled signal advances or delays in comparison of an optimum duty ratio. A delay amount selector responds to the result of the comparison of the delay amount comparator for generating a delay control signal optimizing the delay amount of the cascaded first delay circuits. Thus, the frequency-doubled signal can be automatically controlled to have a optimum duty ratio.

REFERENCES:
patent: 5260608 (1993-11-01), Marbot
patent: 5422835 (1995-06-01), Houle et al.
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5530387 (1996-06-01), Kim
patent: 5801559 (1998-09-01), Sawai et al.
patent: 5933035 (1999-08-01), Bezzant et al.

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