Digital frequency multiplier

Oscillators – Plural oscillators – Cascade or tandem connected

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Details

307220R, 307221R, 328 15, H03B 1900

Patent

active

039709540

ABSTRACT:
A circuit arrangement for multiplying the repetition rate of an input signal by digital techniques is disclosed. A digital counter driven by a high speed clock generates a count proportional to the input period. This count or a different count generated by translating the input count is stored repetitively at the end of each input period. A second counter is used to count the same reference pulses and produce an output pulse when its count equals the stored count.
Alternatively, one of the counters can be reset to a non-zero value at the end of each of its operation cycles, thus allowing a match to be reached in an appropriate output period.

REFERENCES:
patent: 3798564 (1974-03-01), Langham
patent: 3885138 (1975-05-01), Bates

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