Oscillators – Ring oscillators
Reexamination Certificate
1998-05-28
2001-08-28
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C331S00100A, C331S025000, C331S045000, C327S158000, C327S159000
Reexamination Certificate
active
06281759
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a digital frequency generation method and apparatus. The invention is particularly suitable for use to generate a pulse signal, such as a clock signal, but it is not limited exclusively to this. The invention is also particularly suitable for implementing on an integrated circuit, but again, the invention is not limited exclusively to this.
BACKGROUND OF THE INVENTION
There are many applications for which a controllable or variable frequency generator is needed, for example, in mobile communications (mobile telephones), or when it is desired to synchronise two circuits. Other applications include data and clock recovery (when it is desired to generate a clock signal synchronised to a data stream which may include dither).
Particular problems can arise when it is desired to generate an original pulse signal having a frequency which is controllable very finely, for example, in very fine frequency steps. Generally, digital oscillators having a fixed frequency can be implemented relatively easily, for example, based on a crystal or other high Q circuit, but it is difficult to produce a controllable output frequency other than the crystal frequency (or integer division multiples thereof).
Fine frequency control has been achieved digitally using oversampling techniques such as direct digital synthesis, and using phase locked loops. However, direct digital synthesis techniques suffer from the disadvantage that they require an original clock frequency which is very much higher than the output frequency. Moreover, direct digital synthesis requires fairly complex circuitry to implement.
As an example,
FIG. 1
illustrates a general circuit for direct digital synthesis. The output waveform is stored in a read only memory (ROM)
10
, which is addressed by a phase address register
12
. Each time a clock pulse is received from the fixed frequency oscillator
14
, the value in the address register
12
is updated by the adder
16
incrementing the current address value by a phase increment value stored in increment register
18
. The digital output from the ROM
10
is converted to an analogue signal by an output digital to analogue converter (DAC)
20
.
The output frequency depends on the number of address bits in the adder
16
, the increment value stored in register
18
, and the fixed clock frequency. Frequency control is achieved by varying the increment value stored in register
18
, the smallest frequency step achievable being dependent generally on N/F where N is the number of bits in the adder, and F is the fixed frequency. Fine frequency control is obtainable only by using an overly high fixed frequency F, and a relatively high number of arithmetic adder bits N. This requires the use of high speed arithmetic circuitry.
SUMMARY OF THE INVENTION
The present invention has been devised bearing the above problems in mind.
In contrast to the prior art, one aspect of the present invention is to generate an output frequency which has a controllable relationship with an oscillator frequency by using multiple phases of the oscillator signal. The output is provided by selecting a signal from the plurality of phases, and the frequency control is achieved by varying this selection cyclically, so that the output signal may be composed of segments of different phases.
Each time the selection is changed, the period between a pulse of the preceding segment and a pulse of the new segment will be different from the basic period of each phase (i.e. either longer or shorter than the basic period). By controlling the rate at which the different phases are repetitively selected, an output signal can be generated having an effective frequency different from the basic oscillator frequency.
An important advantage of this invention is that it does not require a oscillator frequency which is much higher than the frequency desired to be generated. The generator can output a controlled frequency which is close to the oscillator frequency. Also, multiphase oscillators can be implemented very easily, for example, on an integrated circuit.
Multi-phase oscillators have been used hitherto in data/clock recovery applications, although not for original frequency generation. An example of such an application is illustrated in FIG.
2
. The different phase outputs
22
from a inulti-phase oscillator
24
are fed to a selector switch
26
which is operable to select one of the multiple phase signals
22
as the final output
28
. The switch
26
is controlled by an up/down counter
30
, the value held in the counter controlling which of the multi-phase signals
22
is selected by the switch
26
.
The output
28
is synchronised relative to an incoming pulse signal
32
by means of a phase detector
34
and a loop filter circuit
36
, the output of which controls the up/down counter
30
. The circuit attempts to correct phase differences between the output signal
28
and the incoming signal
32
, by selection of the multi-phase output signals
22
. If the generated output
28
leads the incoming signal
32
, then the counter
30
is controlled to decrement the count value, to thereby control the selector switch
26
to select a respective one of the multi-phased signals
22
having a phase lag. Similarly, if the output signal
28
is lagging behind the incoming signal
32
, then the counter
30
is controlled to increment its count value, to thereby control the selector switch
26
to select a respective one of the multi-phased signals
22
with a more advanced phase.
The above circuit is only effective when the frequency of the incoming signal
32
is the same as, or very close to, the fixed frequency of the oscillator
24
. If the frequencies are slightly different, then the circuit will tend to cycle through the multi-phase outputs to minimise the phase difference.
The circuit of
FIG. 2
may be regarded as simply as an “aligner” for aligning the output from the oscillator
24
with an incoming pulse signal
32
. The output
28
simply mimics a clock signal to match the incoming pulse signal
32
. Therefore, such a circuit is not suitable as a stand-alone, or original, frequency generator because it relies on receiving an input pulse train having the same characteristic frequency as that to be generated.
To the best of the inventor's knowledge, the technique of cyclically selecting the outputs from a multi-phase oscillator has not hitherto been used for original frequency generation.
In one specific aspect, the invention provides a digital frequency generator, comprising:
an oscillator circuit with means for producing multiphase output pulse signals;
switch means for outputting a selected signal from the plurality of multiphase pulse signals from the oscillator circuit; and
cyclic selection means driven by a signal from the oscillator circuit or from the switch means, and operable to control the switch means to vary cyclically the selection of the signal used as the output signal, to thereby generate an output signal having a frequency different from the oscillator frequency.
In a closely related aspect, the invention provides a method of digital frequency generation, comprising:
generating a plurality of multi-phase pulse signals all having a common predetermined frequency; and
cyclically selecting at a controllable or predetermined rate, different ones of the multi-phase pulse signals for output, to thereby generate an output signal having a frequency different from the oscillator frequency.
REFERENCES:
patent: 4684897 (1987-08-01), Richards et al.
patent: 5068628 (1991-11-01), Ghoshal
patent: 5394116 (1995-02-01), Kasturia
patent: 5854576 (1998-12-01), Swan
patent: 0 403 990 A2 (1990-12-01), None
patent: 0 516 379 A2 (1992-12-01), None
Kinkead Arnold
LSI Logic Corporation
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