Digital frequency divider

Details Digital frequency divider Digital frequency divider

2002-02-15

2003-09-09

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000, C327S117000

Reexamination Certificate

active

06618462

ABSTRACT:

FIELD OF INVENTION
The present invention generally relates to divider circuitry and, more particularly, relates to a system and method for fractionally dividing a clock frequency.
BACKGROUND
In modem digital circuitry, such as digital signal processors, it is often advantageous to generate multiple clock signals of various frequencies from a smaller set of reference frequencies. Additionally, some applications call for these multiple generated frequencies to be non-integer multiples of the reference frequency. Furthermore, these applications may also call for each generated frequency to have no common factors with the other generated clock frequencies (i.e., the ratio of each generated frequency to the reference frequency might not share any prime factors with other generated frequencies). In many cases, it is also desirable that the generated frequencies be software or firmware controlled to accommodate different applications.
To date, many solutions exist that employ numerous analog circuits, such as voltage-controlled oscillators (VCO) and phase-locked loops (PLL). However, these circuits are costly to implement due to their relatively large size, power requirements, and sensitivity to electrical as well as physical design rules. In addition to these cumbersome and costly analog circuits, several current approaches allow for the generation of multiple clock frequencies using a single clock frequency as the input clock for multiple clock-dividers. In several of these systems, a clock divider may be easily constructed to divide a reference frequency by powers of two (i.e., 2
n
) or by integer values. However, the complexity of the system increases when the divisor is a non-integer value.
Several approaches exist for non-integer division of clock frequencies, such as a rational-rate multiplier (RRM) approach (e.g., U.S. Pat. No. 5,088,057) or a fractional-frequency divider (FFD) approach (e.g., U.S. Pat. Nos. 5,970,110 and 6,157,694).
In the RRM approach, the reference clock frequency is divided by one of two integer values to produce a frequency higher than the desired frequency or a frequency lower than the desired frequency. The system then switches between these two clock frequencies to produce a desired average clock frequency. Thus, in the RRM approach, the desired clock frequency is composed of two different clock frequencies that “average” to the desired clock frequency. For example, a desired frequency of ⅝ or 0.625 times the input frequency can be created by generating two cycles equal to the reference frequency for every three cycles equal to one-half of the reference frequency. The instantaneous frequency would, therefore, be equal to either the reference clock frequency or half of the reference clock frequency, but the average frequency would be ⅝ the input clock frequency. The inherent limitation of this technique is that the clock appears to jitter by one full clock cycle. Additionally, the peak frequency may be much higher than the average frequency, thereby requiring circuitry utilizing the clock to be designed for higher speed operation than what is actually required.
Another technique is the FFD, as disclosed in U.S. Pat. No. 6,157,694. In the FFD approach, the system maintains multiple copies of the reference clock that differ only in phase, which may be generated in various ways such as multi-phase phase-locked loops (PLL) or multi-tapped delay-locked loops (DLL). For such an approach, each copy of the clock is phase shifted so that the cycle of each of the clocks is equidistant from the cycle of each adjacent clock. Thus, clock cycles may be generated wherein the effective clock frequency is a non-integer multiple of the reference clock frequency. One drawback behind such an approach, however, is that the frequency is divisible by only N+(K/X), wherein N is an integer, X is equal to the number of phase-shifted copies of the input clock and K is less than X−1. Furthermore, a finite-state-machine of moderate complexity is required to count clock cycles and control a clock selector multiplexer (MUX) that is associated with such an approach. Thus, the FFD design assumes computation of the cycle counting and MUX selection to be performed by the user or some other automatic means and input to the state machine.
Another FFD approach may be found in U.S. Pat. No. 5,970,110. Similar to the FFD of U.S. Pat. No. 6,157,694, phase-shifted copies of the input clock are directed to a counter/divider under the control of a state machine. Once again, this approach is limited to division by N+(K/X). Moreover, this approach requires complex state-machine control and pre-computation of the cycle counting behavior. Furthermore, the approach of U.S. Pat. No. 5,970,110 requires frequency doubling and additional memory to function properly for cases where N is less than 2.
Accordingly, there exists a need in the industry for a system and method for a general programmable frequency generator or a general clock frequency divider.
SUMMARY
The present invention provides a system and method for dividing a reference clock signal by a real number, which allows for any desired degree of precision.
Briefly described, in architecture, one embodiment of the system comprises a reference clock operating at a given reference clock frequency, and a frequency-divider circuit configured to divide the reference clock frequency by a real number having an integer portion, a remainder portion, and an error portion. The error portion of the real number allows the system to divide the reference clock frequency by a real number having any desired degree of precision.
The present invention can also be viewed as a method for dividing a reference clock signal by a real number having any desired degree of precision. In this regard, one embodiment of such a method can be broadly summarized as including the steps of receiving a reference clock signal having a reference clock frequency, and dividing the reference clock frequency by a real number having an integer portion, a remainder portion, and an error portion. Again, the error portion of the real number allows for the division of the reference clock frequency by a real number having any desired degree of precision.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.


REFERENCES:
patent: 5088057 (1992-02-01), Amrany et al.
patent: 5970110 (1999-10-01), Li
patent: 6157694 (2000-12-01), Larsson

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